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Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/ke…
…rnel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.
Noteworthy driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the
soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree, we
have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an
optimization, and SCMI now supports the 3.1 version of the
specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
drivers
- Memory controller updates for Tegra, and a few updates for other
platforms"
* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
memory: tegra: Add MC error logging on Tegra186 onward
memory: tegra: Add memory controller channels support
memory: tegra: Add APE memory clients for Tegra234
memory: tegra: Add Tegra234 support
nvme-apple: fix sparse endianess warnings
soc/tegra: pmc: Document core domain fields
soc: qcom: pdr: use static for servreg_* variables
soc: imx: fix semicolon.cocci warnings
soc: renesas: R-Car V3U is R-Car Gen4
soc: imx: add i.MX8MP HDMI blk-ctrl
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
soc: imx: add i.MX8MP HSIO blk-ctrl
soc: imx: imx8m-blk-ctrl: set power device name
soc: qcom: llcc: Add sc8180x and sc8280xp configurations
dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
soc/tegra: pmc: Select REGMAP
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
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147 changes: 147 additions & 0 deletions
147
Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,147 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs | ||
|
|
||
| maintainers: | ||
| - Michael Srba <[email protected]> | ||
|
|
||
| description: | | ||
| This binding describes the dependencies (clocks, resets, power domains) which | ||
| need to be turned on in a sequence before communication over the AHB bus | ||
| becomes possible. | ||
| Additionally, the reg property is used to pass to the driver the location of | ||
| two sadly undocumented registers which need to be poked as part of the sequence. | ||
| The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart | ||
| controllers, a hexagon core, and a clock controller which provides clocks for | ||
| the above. | ||
| properties: | ||
| compatible: | ||
| items: | ||
| - const: qcom,msm8998-ssc-block-bus | ||
| - const: qcom,ssc-block-bus | ||
|
|
||
| reg: | ||
| description: | | ||
| Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 | ||
| registers | ||
| minItems: 2 | ||
| maxItems: 2 | ||
|
|
||
| reg-names: | ||
| items: | ||
| - const: mpm_sscaon_config0 | ||
| - const: mpm_sscaon_config1 | ||
|
|
||
| '#address-cells': | ||
| enum: [ 1, 2 ] | ||
|
|
||
| '#size-cells': | ||
| enum: [ 1, 2 ] | ||
|
|
||
| ranges: true | ||
|
|
||
| clocks: | ||
| minItems: 6 | ||
| maxItems: 6 | ||
|
|
||
| clock-names: | ||
| items: | ||
| - const: xo | ||
| - const: aggre2 | ||
| - const: gcc_im_sleep | ||
| - const: aggre2_north | ||
| - const: ssc_xo | ||
| - const: ssc_ahbs | ||
|
|
||
| power-domains: | ||
| description: Power domain phandles for the ssc_cx and ssc_mx power domains | ||
| minItems: 2 | ||
| maxItems: 2 | ||
|
|
||
| power-domain-names: | ||
| items: | ||
| - const: ssc_cx | ||
| - const: ssc_mx | ||
|
|
||
| resets: | ||
| description: | | ||
| Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the | ||
| branch control register associated with the ssc_xo and ssc_ahbs clocks) | ||
| minItems: 2 | ||
| maxItems: 2 | ||
|
|
||
| reset-names: | ||
| items: | ||
| - const: ssc_reset | ||
| - const: ssc_bcr | ||
|
|
||
| qcom,halt-regs: | ||
| $ref: /schemas/types.yaml#/definitions/phandle-array | ||
| description: describes how to locate the ssc AXI halt register | ||
| items: | ||
| - items: | ||
| - description: Phandle reference to a syscon representing TCSR | ||
| - description: offset for the ssc AXI halt register | ||
|
|
||
| required: | ||
| - compatible | ||
| - reg | ||
| - reg-names | ||
| - '#address-cells' | ||
| - '#size-cells' | ||
| - ranges | ||
| - clocks | ||
| - clock-names | ||
| - power-domains | ||
| - power-domain-names | ||
| - resets | ||
| - reset-names | ||
| - qcom,halt-regs | ||
|
|
||
| additionalProperties: | ||
| type: object | ||
|
|
||
| examples: | ||
| - | | ||
| #include <dt-bindings/clock/qcom,gcc-msm8998.h> | ||
| #include <dt-bindings/clock/qcom,rpmcc.h> | ||
| #include <dt-bindings/power/qcom-rpmpd.h> | ||
| soc { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; | ||
| ssc_ahb_slave: bus@10ac008 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; | ||
| compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; | ||
| reg = <0x10ac008 0x4>, <0x10ac010 0x4>; | ||
| reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; | ||
| clocks = <&xo>, | ||
| <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, | ||
| <&gcc GCC_IM_SLEEP>, | ||
| <&gcc AGGRE2_SNOC_NORTH_AXI>, | ||
| <&gcc SSC_XO>, | ||
| <&gcc SSC_CNOC_AHBS_CLK>; | ||
| clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; | ||
| resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; | ||
| reset-names = "ssc_reset", "ssc_bcr"; | ||
| power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; | ||
| power-domain-names = "ssc_cx", "ssc_mx"; | ||
| qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,52 @@ | ||
| # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/iommu/apple,sart.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
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||
| title: Apple SART DMA address filter | ||
|
|
||
| maintainers: | ||
| - Sven Peter <[email protected]> | ||
|
|
||
| description: | ||
| Apple SART is a simple address filter for DMA transactions. Regions of | ||
| physical memory must be added to the SART's allow list before any | ||
| DMA can target these. Unlike a proper IOMMU no remapping can be done and | ||
| special support in the consumer driver is required since not all DMA | ||
| transactions of a single device are subject to SART filtering. | ||
|
|
||
| SART1 has first been used since at least the A11 (iPhone 8 and iPhone X) | ||
| and allows 36 bit of physical address space and filter entries with sizes | ||
| up to 24 bit. | ||
|
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||
| SART2, first seen in A14 and M1, allows 36 bit of physical address space | ||
| and filter entry size up to 36 bit. | ||
|
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||
| SART3, first seen in M1 Pro/Max, extends both the address space and filter | ||
| entry size to 42 bit. | ||
|
|
||
| properties: | ||
| compatible: | ||
| enum: | ||
| - apple,t6000-sart | ||
| - apple,t8103-sart | ||
|
|
||
| reg: | ||
| maxItems: 1 | ||
|
|
||
| power-domains: | ||
| maxItems: 1 | ||
|
|
||
| required: | ||
| - compatible | ||
| - reg | ||
|
|
||
| additionalProperties: false | ||
|
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||
| examples: | ||
| - | | ||
| iommu@7bc50000 { | ||
| compatible = "apple,t8103-sart"; | ||
| reg = <0x7bc50000 0x4000>; | ||
| }; |
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