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feat: update project tt_um_cejmu_riscv from CEJMU/tt06_tinyrv1
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Commit: defe915e0b6acd64ab23a3e52857420947b1b0ae
Workflow: https://github.com/CEJMU/tt06_tinyrv1/actions/runs/8758341719
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Apr 19, 2024
1 parent 7fe6c00 commit 7f647a9
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6 changes: 3 additions & 3 deletions projects/tt_um_cejmu_riscv/commit_id.json
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@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt06 c74b14ac",
"app": "Tiny Tapeout tt06 7f56a586",
"repo": "https://github.com/CEJMU/tt06_tinyrv1",
"commit": "4296ccf2eb02243b0fc0a7c2dc726749933b268f",
"workflow_url": "https://github.com/CEJMU/tt06_tinyrv1/actions/runs/8728405949",
"commit": "defe915e0b6acd64ab23a3e52857420947b1b0ae",
"workflow_url": "https://github.com/CEJMU/tt06_tinyrv1/actions/runs/8758341719",
"sort_id": 1713388258984,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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8 changes: 4 additions & 4 deletions projects/tt_um_cejmu_riscv/docs/info.md
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Expand Up @@ -7,14 +7,14 @@ You can also include images in this folder and reference them in the markdown. E
512 kb in size, and the combined size of all images must be less than 1 MB.
-->

## How it works
# How it works

TODO Will cover how the project works
The project consist of a RISC-V VHDL Model and supports the [Tiny RV1 ISA](https://github.com/cbatten/ece4750-tinyrv-isa) without MUL. In addition AND and XOR are supported.

## How to test

TODO Will explain how to test
To test our design you will need to use external hardware.

## External hardware

List external hardware used in your project (e.g. PMOD, LED display, etc), if any
To use our design you will need to use the provided spi_slave_tt06_with_memory and synthesize it for an 12 MHz FPGA.
58 changes: 29 additions & 29 deletions projects/tt_um_cejmu_riscv/info.yaml
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@@ -1,11 +1,11 @@
# Tiny Tapeout project information
project:
title: "CEJMU" # Project title
author: "CEJMU" # Your name
discord: "CEJMU" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "CEJMU" # One line description of what your project does
title: "TinyRV1 CPU" # Project title
author: "Prof. Dr. Matthias Jung, Jonathan Hager, Philipp Wetzstein" # Your name
discord: "myzinsky" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "TinyRV1 compliant CPU that has to be attached to an external SPI memory. The ISA is described in the documentation" # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)
clock_hz: 12000000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "3x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
Expand All @@ -20,34 +20,34 @@ project:
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: ""
ui[1]: ""
ui[2]: ""
ui[3]: ""
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""
ui[0]: "SPI MISO"
ui[1]: "unused"
ui[2]: "unused"
ui[3]: "unused"
ui[4]: "unused"
ui[5]: "unused"
ui[6]: "unused"
ui[7]: "unused"

# Outputs
uo[0]: ""
uo[1]: ""
uo[2]: ""
uo[3]: ""
uo[4]: ""
uo[5]: ""
uo[6]: ""
uo[7]: ""
uo[0]: "SPI MOSI"
uo[1]: "SPI SCLK"
uo[2]: "SPI CS"
uo[3]: "Register_1(0)"
uo[4]: "Register_1(1)"
uo[5]: "Register_1(2)"
uo[6]: "Register_1(3)"
uo[7]: "Register_1(4)"

# Bidirectional pins
uio[0]: ""
uio[1]: ""
uio[2]: ""
uio[3]: ""
uio[4]: ""
uio[5]: ""
uio[6]: ""
uio[7]: ""
uio[0]: "Register_1(5)"
uio[1]: "Register_1(6)"
uio[2]: "Register_1(7)"
uio[3]: "Register_1(8)"
uio[4]: "Register_1(9)"
uio[5]: "Register_1(10)"
uio[6]: "Register_1(11)"
uio[7]: "Register_1(12)"

# Do not change!
yaml_version: 6
2 changes: 1 addition & 1 deletion projects/tt_um_cejmu_riscv/stats/metrics.csv
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@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_cejmu_riscv,wokwi,flow completed,0h10m49s0ms,0h8m34s0ms,115830.32666687433,0.1148576576,57915.163333437165,72.59,78.289,820.47,6136,0,0,0,0,0,0,0,4,4,0,-1,-1,255500,52945,-3.36,-1,-1,-1,-1,-3900.56,-1,-1,-1,-1,162527757.0,0.0,68.1,57.74,40.97,12.35,-1,3759,8212,259,4712,0,0,0,5069,12,74,76,104,351,165,8,2335,1341,1337,18,2585,1577,75,2459,6652,13348,110873.8368,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.73,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_cejmu_riscv,wokwi,flow completed,0h9m46s0ms,0h7m42s0ms,115011.92237442949,0.1148576576,57505.96118721474,72.75,77.9335,782.41,6143,0,0,0,0,0,0,0,36,10,0,-1,-1,259606,53392,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,167848755.0,0.0,68.29,58.25,43.4,11.85,-1,3821,8290,259,4728,0,0,0,5131,14,74,75,98,412,166,7,2331,1341,1337,21,2588,1577,50,2371,6605,13191,110873.8368,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,84.33,11.858176212498519,83.33,1,50,153.18,153.6,0.3,1,10,0.73,0,sky130_fd_sc_hd,AREA 0
99 changes: 51 additions & 48 deletions projects/tt_um_cejmu_riscv/stats/synthesis-stats.txt
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Expand Up @@ -3,77 +3,80 @@

=== tt_um_cejmu_riscv ===

Number of wires: 6120
Number of wire bits: 6155
Number of wires: 6127
Number of wire bits: 6162
Number of public wires: 1415
Number of public wire bits: 1450
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 6136
Number of cells: 6143
sky130_fd_sc_hd__a2111o_2 2
sky130_fd_sc_hd__a211o_2 15
sky130_fd_sc_hd__a211oi_2 5
sky130_fd_sc_hd__a211o_2 14
sky130_fd_sc_hd__a211oi_2 2
sky130_fd_sc_hd__a21bo_2 3
sky130_fd_sc_hd__a21o_2 38
sky130_fd_sc_hd__a21boi_2 3
sky130_fd_sc_hd__a21o_2 41
sky130_fd_sc_hd__a21oi_2 54
sky130_fd_sc_hd__a221o_2 71
sky130_fd_sc_hd__a22o_2 80
sky130_fd_sc_hd__a22oi_2 4
sky130_fd_sc_hd__a2bb2o_2 5
sky130_fd_sc_hd__a311o_2 2
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 24
sky130_fd_sc_hd__a31oi_2 3
sky130_fd_sc_hd__a221o_2 73
sky130_fd_sc_hd__a22o_2 83
sky130_fd_sc_hd__a22oi_2 8
sky130_fd_sc_hd__a2bb2o_2 6
sky130_fd_sc_hd__a311o_2 1
sky130_fd_sc_hd__a31o_2 23
sky130_fd_sc_hd__a31oi_2 2
sky130_fd_sc_hd__a32o_2 7
sky130_fd_sc_hd__a41o_2 1
sky130_fd_sc_hd__and2_2 69
sky130_fd_sc_hd__a41oi_2 1
sky130_fd_sc_hd__and2_2 72
sky130_fd_sc_hd__and2b_2 28
sky130_fd_sc_hd__and3_2 71
sky130_fd_sc_hd__and3b_2 8
sky130_fd_sc_hd__and4_2 6
sky130_fd_sc_hd__and4b_2 3
sky130_fd_sc_hd__and3_2 69
sky130_fd_sc_hd__and3b_2 14
sky130_fd_sc_hd__and4_2 4
sky130_fd_sc_hd__and4b_2 1
sky130_fd_sc_hd__and4bb_2 2
sky130_fd_sc_hd__buf_1 1629
sky130_fd_sc_hd__buf_2 3
sky130_fd_sc_hd__conb_1 9
sky130_fd_sc_hd__dfrtp_2 1130
sky130_fd_sc_hd__dfstp_2 2
sky130_fd_sc_hd__dfxtp_2 208
sky130_fd_sc_hd__inv_2 34
sky130_fd_sc_hd__mux2_2 1353
sky130_fd_sc_hd__mux4_2 533
sky130_fd_sc_hd__nand2_2 52
sky130_fd_sc_hd__nand3_2 8
sky130_fd_sc_hd__nand3b_2 4
sky130_fd_sc_hd__nand4_2 1
sky130_fd_sc_hd__nor2_2 118
sky130_fd_sc_hd__inv_2 41
sky130_fd_sc_hd__mux2_2 1350
sky130_fd_sc_hd__mux4_2 537
sky130_fd_sc_hd__nand2_2 68
sky130_fd_sc_hd__nand3_2 5
sky130_fd_sc_hd__nand3b_2 1
sky130_fd_sc_hd__nand4_2 2
sky130_fd_sc_hd__nor2_2 103
sky130_fd_sc_hd__nor2b_2 3
sky130_fd_sc_hd__nor3_2 11
sky130_fd_sc_hd__nor4_2 3
sky130_fd_sc_hd__nor3_2 8
sky130_fd_sc_hd__nor4_2 2
sky130_fd_sc_hd__o2111a_2 1
sky130_fd_sc_hd__o211a_2 42
sky130_fd_sc_hd__o211ai_2 3
sky130_fd_sc_hd__o21a_2 122
sky130_fd_sc_hd__o21ai_2 22
sky130_fd_sc_hd__o2111ai_2 1
sky130_fd_sc_hd__o211a_2 40
sky130_fd_sc_hd__o211ai_2 2
sky130_fd_sc_hd__o21a_2 119
sky130_fd_sc_hd__o21ai_2 21
sky130_fd_sc_hd__o21ba_2 58
sky130_fd_sc_hd__o21bai_2 5
sky130_fd_sc_hd__o221a_2 3
sky130_fd_sc_hd__o21bai_2 1
sky130_fd_sc_hd__o221a_2 5
sky130_fd_sc_hd__o22a_2 6
sky130_fd_sc_hd__o22ai_2 2
sky130_fd_sc_hd__o2bb2a_2 2
sky130_fd_sc_hd__o311a_2 4
sky130_fd_sc_hd__o31a_2 9
sky130_fd_sc_hd__o31ai_2 2
sky130_fd_sc_hd__or2_2 71
sky130_fd_sc_hd__or2b_2 59
sky130_fd_sc_hd__o22ai_2 1
sky130_fd_sc_hd__o2bb2a_2 1
sky130_fd_sc_hd__o311a_2 5
sky130_fd_sc_hd__o31a_2 7
sky130_fd_sc_hd__o31ai_2 6
sky130_fd_sc_hd__o41a_2 1
sky130_fd_sc_hd__or2_2 66
sky130_fd_sc_hd__or2b_2 58
sky130_fd_sc_hd__or3_2 31
sky130_fd_sc_hd__or3b_2 23
sky130_fd_sc_hd__or4_2 26
sky130_fd_sc_hd__or4b_2 12
sky130_fd_sc_hd__or3b_2 17
sky130_fd_sc_hd__or4_2 29
sky130_fd_sc_hd__or4b_2 11
sky130_fd_sc_hd__or4bb_2 3
sky130_fd_sc_hd__xnor2_2 10
sky130_fd_sc_hd__xor2_2 17
sky130_fd_sc_hd__xnor2_2 18
sky130_fd_sc_hd__xor2_2 20

Chip area for module '\tt_um_cejmu_riscv': 78614.147200
Chip area for module '\tt_um_cejmu_riscv': 78786.812800

Binary file modified projects/tt_um_cejmu_riscv/tt_um_cejmu_riscv.gds
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41 changes: 21 additions & 20 deletions projects/tt_um_cejmu_riscv/tt_um_cejmu_riscv.lef
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Expand Up @@ -63,7 +63,7 @@ MACRO tt_um_cejmu_riscv
PIN rst_n
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.196500 ;
ANTENNAGATEAREA 0.213000 ;
PORT
LAYER met4 ;
RECT 151.190 224.760 151.490 225.760 ;
Expand Down Expand Up @@ -286,7 +286,7 @@ MACRO tt_um_cejmu_riscv
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 51.830 224.760 52.130 225.760 ;
Expand Down Expand Up @@ -336,7 +336,7 @@ MACRO tt_um_cejmu_riscv
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 33.430 224.760 33.730 225.760 ;
Expand All @@ -345,7 +345,7 @@ MACRO tt_um_cejmu_riscv
PIN uo_out[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.795200 ;
ANTENNADIFFAREA 1.590400 ;
PORT
LAYER met4 ;
RECT 88.630 224.760 88.930 225.760 ;
Expand Down Expand Up @@ -383,7 +383,7 @@ MACRO tt_um_cejmu_riscv
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 73.910 224.760 74.210 225.760 ;
Expand All @@ -393,7 +393,7 @@ MACRO tt_um_cejmu_riscv
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 70.230 224.760 70.530 225.760 ;
Expand All @@ -403,7 +403,7 @@ MACRO tt_um_cejmu_riscv
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 66.550 224.760 66.850 225.760 ;
Expand All @@ -413,7 +413,7 @@ MACRO tt_um_cejmu_riscv
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNADIFFAREA 0.891000 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 62.870 224.760 63.170 225.760 ;
Expand All @@ -423,11 +423,11 @@ MACRO tt_um_cejmu_riscv
LAYER li1 ;
RECT 2.760 2.635 506.000 223.125 ;
LAYER met1 ;
RECT 2.460 1.060 506.300 223.680 ;
RECT 2.460 2.080 506.300 223.280 ;
LAYER met2 ;
RECT 3.780 1.030 504.520 224.245 ;
RECT 4.230 2.050 504.980 224.245 ;
LAYER met3 ;
RECT 3.950 2.555 501.795 224.225 ;
RECT 3.950 2.555 504.095 224.225 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.760 ;
RECT 8.370 224.360 10.950 224.760 ;
Expand Down Expand Up @@ -471,15 +471,16 @@ MACRO tt_um_cejmu_riscv
RECT 148.210 224.360 150.790 224.760 ;
RECT 151.890 224.360 154.470 224.760 ;
RECT 155.570 224.360 158.150 224.760 ;
RECT 159.250 224.360 474.425 224.760 ;
RECT 3.975 223.680 474.425 224.360 ;
RECT 3.975 4.255 17.880 223.680 ;
RECT 20.280 4.255 94.680 223.680 ;
RECT 97.080 4.255 171.480 223.680 ;
RECT 173.880 4.255 248.280 223.680 ;
RECT 250.680 4.255 325.080 223.680 ;
RECT 327.480 4.255 401.880 223.680 ;
RECT 404.280 4.255 474.425 223.680 ;
RECT 159.250 224.360 481.785 224.760 ;
RECT 3.975 223.680 481.785 224.360 ;
RECT 3.975 7.655 17.880 223.680 ;
RECT 20.280 7.655 94.680 223.680 ;
RECT 97.080 7.655 171.480 223.680 ;
RECT 173.880 7.655 248.280 223.680 ;
RECT 250.680 7.655 325.080 223.680 ;
RECT 327.480 7.655 401.880 223.680 ;
RECT 404.280 7.655 478.680 223.680 ;
RECT 481.080 7.655 481.785 223.680 ;
END
END tt_um_cejmu_riscv
END LIBRARY
Expand Down
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