Commits

Breadcrumbs

History for

onmaster

User selector

All users

Datepicker

All time

Commit History

Commits on Jun 25, 2019

• merge master into vega

  

  Pasquale Davide Schiavone

  committed
  e5940cf

  Copy full SHA for e5940cf

Commits on May 24, 2019

• Dedicate tb tiscv sv models to Questa

  florent-gwt

  committed
  a303717

  Copy full SHA for a303717

Commits on Apr 15, 2019

• Remove references to old debug unit

  bluewww

  committed
  eb44691

  Copy full SHA for eb44691

Commits on Jan 21, 2019

• merge master

  davideschiavone

  committed
  40665c1

  Copy full SHA for 40665c1

Commits on Jan 11, 2019

• updated src_files

  

  Davide Rossi

  committed
  28bb51d

  Copy full SHA for 28bb51d

Commits on Jan 10, 2019

• updated src_files.yml

  

  Davide Rossi

  committed
  6db9331

  Copy full SHA for 6db9331

Commits on Nov 7, 2018

• Add ram_wrapper for FPGA

  owenchj0

  committed
  d2e15e5

  Copy full SHA for d2e15e5

Commits on Oct 23, 2018

• ✏️ Fix syntax errors from merge

  

  Stefan Mach

  committed
  1384ccd

  Copy full SHA for 1384ccd

Commits on Jul 11, 2018

• started including pmp registers

  davideschiavone

  committed
  e83b0f1

  Copy full SHA for e83b0f1

• update name of the PMP module

  davideschiavone

  committed
  253f553

  Copy full SHA for 253f553

• Merge remote-tracking branch 'origin' into tb_riscv

  davideschiavone

  committed
  bc30fcd

  Copy full SHA for bc30fcd

Commits on Jul 5, 2018

• Inserted register file TEST wrapper, for enabling MBIST

  

  Igor Loi

  committed
  4b4078e

  Copy full SHA for 4b4078e

Commits on Jun 19, 2018

• Change dir structure and add files to docs folder

  florent-gwt

  committed
  b842d0c

  Copy full SHA for b842d0c

Commits on Mar 2, 2018

• start integration of tb_riscv: core-verification modules

  davideschiavone

  committed
  0a98b70

  Copy full SHA for 0a98b70

Commits on Feb 15, 2018

• updated: skypped tracer in synth

  

  IGOR LOI

  committed
  26875be

  Copy full SHA for 26875be

Commits on Dec 4, 2017

• removed simchecker

  

  Pasquale Davide Schiavone

  committed
  610bb53

  Copy full SHA for 610bb53

Commits on Sep 6, 2017

• added support for gf22

  

  Pasquale Davide Schiavone

  committed
  f8048a0

  Copy full SHA for f8048a0

Commits on Aug 2, 2017

• fetch fifo in separate file

  

  Pasquale Davide Schiavone

  committed
  807a0f3

  Copy full SHA for 807a0f3

Commits on Apr 27, 2017

• updated src yml file

  

  Igor Loi

  committed
  b6f41dc

  Copy full SHA for b6f41dc

Commits on Apr 19, 2017

• reworked interrupt controller

  

  Pasquale Davide Schiavone

  committed
  a83f82e

  Copy full SHA for a83f82e

Commits on Mar 22, 2017

• fixed src file to new register file name

  gautschimi

  committed
  567593f

  Copy full SHA for 567593f

• renamed last files of riscv to have a consistent naming

  gautschimi

  committed
  cfcec67

  Copy full SHA for cfcec67

Commits on Mar 15, 2017

• Merge branch 'master' into verilator

  

  Florian Zaruba

  committed
  df575ad

  Copy full SHA for df575ad

Commits on Mar 8, 2017

• updated cammel file

  

  IGOR LOI

  committed
  bad97b8

  Copy full SHA for bad97b8

• Reverted prefetcher it creates long comb path, i am working on an alternative solution

  

  IGOR LOI

  committed
  ecf1ddc

  Copy full SHA for ecf1ddc

Commits on Feb 2, 2017

• added parameters to riscv core to configure with and without fpu

  gautschimi

  committed
  58a680c

  Copy full SHA for 58a680c

Commits on Jan 25, 2017

• some initial work for fp_integration in pulpino

  gautschimi

  committed
  8e02c65

  Copy full SHA for 8e02c65

Commits on Dec 23, 2016

• updated riscv core with apu extensions

  gautschimi

  committed
  d77fbd3

  Copy full SHA for d77fbd3

Commits on Sep 28, 2016

• added basic ALU with minimal functions, APU perfcounters and support for all DSP APUs

  

  Lukas Mueller

  committed
  8b20fbf

  Copy full SHA for 8b20fbf

Commits on Sep 15, 2016

• updated src_files.yml with apu-related files

  

  Lukas Mueller

  committed
  a81fecd

  Copy full SHA for a81fecd

Commits on Jun 29, 2016

• Correctly renamed latch based register file

  

  Florian Zaruba

  committed
  99b5ada

  Copy full SHA for 99b5ada

Commits on Jun 23, 2016

• Adding more verbosity to prefetch shift entries, implicit construct not working for verilator

  

  Florian Zaruba

  committed
  a2244aa

  Copy full SHA for a2244aa

Commits on Jun 15, 2016

• Renaming files to match module name

  

  Flo Zaruba

  committed
  1742265

  Copy full SHA for 1742265

Commits on Jun 3, 2016

• moved to package based riscv core

  gautschimi

  committed
  8a52246

  Copy full SHA for 8a52246

Commits on Apr 1, 2016

• Add proper targets for sub-ips

  atraber

  committed
  a6976b4

  Copy full SHA for a6976b4

Pagination

Previous

Next