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axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedJan 15, 2021 -
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riscv-gnu-toolchain Public
Forked from riscv-collab/riscv-gnu-toolchainGNU toolchain for RISC-V, including GCC
C Other UpdatedOct 3, 2019 -
riscv-none-gcc Public
Forked from ilg-archived/riscv-none-gccThe GNU MCU Eclipse RISC-V Embedded GCC
C GNU General Public License v2.0 UpdatedSep 27, 2019 -
riscv-dv Public
Forked from chipsalliance/riscv-dvSV/UVM based instruction generator for RISC-V processor verification
SystemVerilog Apache License 2.0 UpdatedSep 14, 2019 -
e200_opensource Public
Forked from SI-RISCV/e200_opensourceThe Ultra-Low Power RISC Core
Verilog Apache License 2.0 UpdatedSep 1, 2019 -
rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedAug 28, 2019 -
ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedAug 26, 2019 -
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picorv32 Public
Forked from YosysHQ/picorv32PicoRV32 - A Size-Optimized RISC-V CPU
Verilog UpdatedAug 9, 2019 -
riscv Public
Forked from openhwgroup/cv32e40pRISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
SystemVerilog Other UpdatedAug 8, 2019 -
lowrisc-chip Public
Forked from lowRISC/lowrisc-chipThe root repo for lowRISC project and FPGA demos.
SystemVerilog Other UpdatedJul 16, 2019 -
pulpino Public
Forked from pulp-platform/pulpinoAn open-source microcontroller system based on RISC-V
C Other UpdatedJul 3, 2019 -
ri5cy_gnu_toolchain Public
Forked from pulp-platform/ri5cy_gnu_toolchainMakefile UpdatedMay 21, 2019 -
riscv-tools Public
Forked from riscv-software-src/riscv-toolsRISC-V Tools (ISA Simulator and Tests)
Shell UpdatedApr 2, 2019 -
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cacti Public
Forked from HewlettPackard/cactiAn integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
C++ UpdatedJun 19, 2017