[new for sdhci]

klaas019 · Mar 19, 2019 · 782352d · 782352d
1 parent 1997b6f
commit 782352d
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Showing 6 changed files with 58 additions and 36 deletions.
diff --git a/arch/arm/mach-aspeed/aspeed-reset.c b/arch/arm/mach-aspeed/aspeed-reset.c
@@ -109,15 +109,18 @@ struct aspeed_reset_config {
 
 #ifdef CONFIG_MACH_ASPEED_G6
 static struct aspeed_reset_config ast2600_reset[] = {
+	{ "eMMC", ASPEED_SCU_BASE + 0x40, BIT(16) },
 	{ "MAC1", ASPEED_SCU_BASE + 0x40, BIT(11) },
 	{ "MAC2", ASPEED_SCU_BASE + 0x40, BIT(12) },
+	{ "SDIO", ASPEED_SCU_BASE + 0x50, BIT(24) },	
 	{ "MAC3", ASPEED_SCU_BASE + 0x50, BIT(20) },
 	{ "MAC4", ASPEED_SCU_BASE + 0x50, BIT(21) },
 	{ "MDIO", ASPEED_SCU_BASE + 0x50, BIT(3) },
 	{ "I2C", ASPEED_SCU_BASE + 0x50, BIT(2) },
 };
 #elif defined(CONFIG_MACH_ASPEED_G4) || defined(CONFIG_MACH_ASPEED_G5)
 static struct aspeed_reset_config ast2500_reset[] = {
+	{ "SDIO", ASPEED_SCU_BASE + 0x04, BIT(16) },
 	{ "MAC1", ASPEED_SCU_BASE + 0x04, BIT(11) },
 	{ "MAC2", ASPEED_SCU_BASE + 0x04, BIT(12) },
 	{ "I2C", ASPEED_SCU_BASE + 0x04, BIT(2) },

diff --git a/arch/arm/mach-aspeed/ast-bmc-scu.c b/arch/arm/mach-aspeed/ast-bmc-scu.c
@@ -173,7 +173,6 @@ ast_scu_init_usb_port1(void)
 	ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_USB20, AST_SCU_RESET);
 }
 
-
 extern void
 ast_scu_init_usb_port2(void)
 {
@@ -189,38 +188,6 @@ ast_scu_init_usb_port2(void)
 }
 #endif
 
-#ifdef SCU_RESET_SD
-#define SCU_CLK_SD_DIV(x)			(x << 12)
-#define SCU_CLK_SD_MASK				(0x7 << 12)
-
-extern void
-ast_scu_init_sdhci(void)
-{
-	//SDHCI Host's Clock Enable and Reset
-	ast_scu_write(ast_scu_read(AST_SCU_RESET) | SCU_RESET_SD, AST_SCU_RESET);
-
-	ast_scu_write(ast_scu_read(AST_SCU_CLK_STOP) & ~SCU_SDCLK_STOP_EN, AST_SCU_CLK_STOP);
-	mdelay(10);
-
-	ast_scu_write(ast_scu_read(AST_SCU_CLK_SEL) | SCU_CLK_SD_EN, AST_SCU_CLK_SEL);
-	mdelay(10);
-
-#ifdef CONFIG_ARCH_AST3200
-	// SDCLK = H-PLL / 12
-	ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_SD_MASK) | SCU_CLK_SD_DIV(7), 
-		AST_SCU_CLK_SEL);
-#else
-	// SDCLK = G4  H-PLL / 4, G5 = H-PLL /8
-	ast_scu_write((ast_scu_read(AST_SCU_CLK_SEL) & ~SCU_CLK_SD_MASK) | SCU_CLK_SD_DIV(1), 
-		AST_SCU_CLK_SEL);
-#endif 
-
-	mdelay(10);
-
-	ast_scu_write(ast_scu_read(AST_SCU_RESET) & ~SCU_RESET_SD, AST_SCU_RESET);
-}
-#endif
-
 extern void
 ast_scu_init_pwm_tacho(void)
 {

diff --git a/arch/arm/mach-aspeed/board.c b/arch/arm/mach-aspeed/board.c
@@ -130,13 +130,45 @@ int board_eth_init(bd_t *bd)
 
 int board_mmc_init(bd_t *bis)
 {
+	char *ctrl0_name, *clk_name;;
+
 	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
 	u8 i;
 
-	ast_scu_init_sdhci();
-	ast_scu_multi_func_sdhc_slot(3);
+	//ast2600
+//	ctrl0_name = "emmc";
+//	ctrl1_name = "sdio";
+
+	//ast2500 
+	ctrl0_name = "SDIO";
+	clk_name = "SD";
+
+	aspeed_reset_assert(ctrl0_name);
+
+	aspeed_clk_enable(ctrl0_name);
+	mdelay(10);	
+	aspeed_clk_enable(clk_name);
+
+	mdelay(10);
+
+	aspeed_set_sd_clk_rate();
+
+	mdelay(10);
+
+	aspeed_reset_deassert(ctrl0_name);
 
 	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		switch(i) {
+			case 0:
+				ctrl0_name = "SDIO0";
+				aspeed_pinctrl_group_set(ctrl0_name);
+				break;
+			case 1:
+				ctrl0_name = "SDIO1";
+				aspeed_pinctrl_group_set(ctrl0_name);
+				break;
+		};
+
 		if (ast_sdhi_init(mmc_base_address[i], aspeed_get_sd_clk_rate(), 100000))
 			return 1;
 	}

diff --git a/arch/arm/mach-aspeed/clk_aspeed.c b/arch/arm/mach-aspeed/clk_aspeed.c
@@ -853,6 +853,20 @@ extern u32 aspeed_get_lpc_host_clk_rate(void)
 }
 #endif
 
+#define AST_SCU_CLK_SEL				0x08		/*	clock selection register	*/
+
+#define SCU_CLK_SD_DIV(x)			(x << 12)
+#define SCU_CLK_SD_MASK				(0x7 << 12)
+
+extern void aspeed_set_sd_clk_rate(void)
+{
+	// SDCLK = G4  H-PLL / 4, G5 = H-PLL /8
+	u32 rate = readl(ASPEED_SCU_BASE + ASPEED_CLK_SELECT);
+
+	writel((rate & ~SCU_CLK_SD_MASK) | SCU_CLK_SD_DIV(1), 
+			ASPEED_SCU_BASE + AST_SCU_CLK_SEL);
+}
+
 extern u32 aspeed_get_sd_clk_rate(void)
 {
 	u32 hpll = aspeed_get_hpll_clk_rate();
@@ -887,6 +901,9 @@ static struct aspeed_clock ast2600_clk[] = {
 static struct aspeed_clock ast2500_clk[] = {
 	{ "MAC1", ASPEED_SCU_BASE + 0x0C, BIT(20), 0 },
 	{ "MAC2", ASPEED_SCU_BASE + 0x0C, BIT(21), 0 },
+	{ "SDIO", ASPEED_SCU_BASE + 0x0C, BIT(27), 0 },	
+	{ "SD", ASPEED_SCU_BASE + 0x08, BIT(15), 1 },
+
 };
 #endif
 

diff --git a/arch/arm/mach-aspeed/include/mach/clk_aspeed.h b/arch/arm/mach-aspeed/include/mach/clk_aspeed.h
@@ -8,5 +8,6 @@ extern u32 aspeed_get_mpll_clk_rate(void);
 extern u32 aspeed_get_p_clk_rate(void);
 extern u32 aspeed_get_sd_clk_rate(void);
 extern void aspeed_clk_enable(char *ctrl_name);
+extern void aspeed_set_sd_clk_rate(void);
 
 #endif
diff --git a/arch/arm/mach-aspeed/pinctrl_aspeed.c b/arch/arm/mach-aspeed/pinctrl_aspeed.c
@@ -164,9 +164,11 @@ static struct aspeed_pinctrl_group_config ast2500_pin_groups[] = {
 	{ "I2C12", ASPEED_SCU_BASE + 0x90, BIT(25), ASPEED_SCU_BASE + 0x90, BIT(0) },
 	{ "I2C13", ASPEED_SCU_BASE + 0x90, BIT(26), ASPEED_SCU_BASE + 0x90, BIT(0) },
 	{ "I2C14", ASPEED_SCU_BASE + 0x90, BIT(27), 0, 0 },
+	{ "SDIO1", ASPEED_SCU_BASE + 0x90, BIT(1), 0, 0 },	
+	{ "SDIO0", ASPEED_SCU_BASE + 0x90, BIT(0), 0, 0 },
 };
 #else
-#err "No define for clk enable"xx
+#err "No define for clk enable"
 #endif
 
 extern void aspeed_pinctrl_group_set(char *group_name)