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MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler
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In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Huacai Chen <[email protected]>
Cc: Jiaxun Yang <[email protected]>
Cc: [email protected]
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paulburton committed Oct 7, 2019
1 parent ae4cd0b commit 12dbb04
Showing 1 changed file with 2 additions and 0 deletions.
2 changes: 2 additions & 0 deletions arch/mips/kernel/genex.S
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/sync.h>
#include <asm/war.h>
#include <asm/thread_info.h>

Expand Down Expand Up @@ -353,6 +354,7 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp)

#ifdef CONFIG_SMP
1: PTR_LA k0, ejtag_debug_buffer_spinlock
__SYNC(full, loongson3_war)
ll k0, 0(k0)
bnez k0, 1b
PTR_LA k0, ejtag_debug_buffer_spinlock
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