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drm/vc4: Demote user-accessible DRM_ERROR paths to DRM_DEBUG.
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Userspace shouldn't be able to spam dmesg by passing bad arguments.
This has particularly become an issues since we started using a bad
argument to set_tiling to detect if set_tiling was supported.

Signed-off-by: Eric Anholt <[email protected]>
Fixes: 8375311 ("drm/vc4: Add get/set tiling ioctls.")
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Boris Brezillon <[email protected]>
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@anholt
anholt committed Aug 8, 2017
1 parent 1d5494e commit fb95992
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Showing 6 changed files with 108 additions and 108 deletions.
14 changes: 7 additions & 7 deletions drivers/gpu/drm/vc4/vc4_bo.c
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Original file line number Diff line number Diff line change
Expand Up @@ -482,7 +482,7 @@ vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags)
struct vc4_bo *bo = to_vc4_bo(obj);

if (bo->validated_shader) {
DRM_ERROR("Attempting to export shader BO\n");
DRM_DEBUG("Attempting to export shader BO\n");
return ERR_PTR(-EINVAL);
}

Expand All @@ -503,7 +503,7 @@ int vc4_mmap(struct file *filp, struct vm_area_struct *vma)
bo = to_vc4_bo(gem_obj);

if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
return -EINVAL;
}

Expand All @@ -528,7 +528,7 @@ int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
struct vc4_bo *bo = to_vc4_bo(obj);

if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
return -EINVAL;
}

Expand All @@ -540,7 +540,7 @@ void *vc4_prime_vmap(struct drm_gem_object *obj)
struct vc4_bo *bo = to_vc4_bo(obj);

if (bo->validated_shader) {
DRM_ERROR("mmaping of shader BOs not allowed.\n");
DRM_DEBUG("mmaping of shader BOs not allowed.\n");
return ERR_PTR(-EINVAL);
}

Expand Down Expand Up @@ -594,7 +594,7 @@ int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,

gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -EINVAL;
}

Expand Down Expand Up @@ -698,7 +698,7 @@ int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,

gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -ENOENT;
}
bo = to_vc4_bo(gem_obj);
Expand Down Expand Up @@ -729,7 +729,7 @@ int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,

gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -ENOENT;
}
bo = to_vc4_bo(gem_obj);
Expand Down
10 changes: 5 additions & 5 deletions drivers/gpu/drm/vc4/vc4_gem.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -659,7 +659,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
/* See comment on bo_index for why we have to check
* this.
*/
DRM_ERROR("Rendering requires BOs to validate\n");
DRM_DEBUG("Rendering requires BOs to validate\n");
return -EINVAL;
}

Expand Down Expand Up @@ -690,7 +690,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
handles[i]);
if (!bo) {
DRM_ERROR("Failed to look up GEM BO %d: %d\n",
DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
i, handles[i]);
ret = -EINVAL;
spin_unlock(&file_priv->table_lock);
Expand Down Expand Up @@ -728,7 +728,7 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
args->shader_rec_count >= (UINT_MAX /
sizeof(struct vc4_shader_state)) ||
temp_size < exec_size) {
DRM_ERROR("overflow in exec arguments\n");
DRM_DEBUG("overflow in exec arguments\n");
ret = -EINVAL;
goto fail;
}
Expand Down Expand Up @@ -973,7 +973,7 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data,

gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -EINVAL;
}
bo = to_vc4_bo(gem_obj);
Expand Down Expand Up @@ -1008,7 +1008,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
int ret = 0;

if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags);
return -EINVAL;
}

Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/vc4/vc4_kms.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -169,7 +169,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
gem_obj = drm_gem_object_lookup(file_priv,
mode_cmd->handles[0]);
if (!gem_obj) {
DRM_ERROR("Failed to look up GEM BO %d\n",
DRM_DEBUG("Failed to look up GEM BO %d\n",
mode_cmd->handles[0]);
return ERR_PTR(-ENOENT);
}
Expand Down
40 changes: 20 additions & 20 deletions drivers/gpu/drm/vc4/vc4_render_cl.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -378,14 +378,14 @@ static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);

if (surf->offset > obj->base.size) {
DRM_ERROR("surface offset %d > BO size %zd\n",
DRM_DEBUG("surface offset %d > BO size %zd\n",
surf->offset, obj->base.size);
return -EINVAL;
}

if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
render_tiles_stride * args->max_y_tile + args->max_x_tile) {
DRM_ERROR("MSAA tile %d, %d out of bounds "
DRM_DEBUG("MSAA tile %d, %d out of bounds "
"(bo size %zd, offset %d).\n",
args->max_x_tile, args->max_y_tile,
obj->base.size,
Expand All @@ -401,7 +401,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
struct drm_vc4_submit_rcl_surface *surf)
{
if (surf->flags != 0 || surf->bits != 0) {
DRM_ERROR("MSAA surface had nonzero flags/bits\n");
DRM_DEBUG("MSAA surface had nonzero flags/bits\n");
return -EINVAL;
}

Expand All @@ -415,7 +415,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;

if (surf->offset & 0xf) {
DRM_ERROR("MSAA write must be 16b aligned.\n");
DRM_DEBUG("MSAA write must be 16b aligned.\n");
return -EINVAL;
}

Expand All @@ -437,7 +437,7 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
int ret;

if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
DRM_ERROR("Extra flags set\n");
DRM_DEBUG("Extra flags set\n");
return -EINVAL;
}

Expand All @@ -453,12 +453,12 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,

if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
if (surf == &exec->args->zs_write) {
DRM_ERROR("general zs write may not be a full-res.\n");
DRM_DEBUG("general zs write may not be a full-res.\n");
return -EINVAL;
}

if (surf->bits != 0) {
DRM_ERROR("load/store general bits set with "
DRM_DEBUG("load/store general bits set with "
"full res load/store.\n");
return -EINVAL;
}
Expand All @@ -473,19 +473,19 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
DRM_ERROR("Unknown bits in load/store: 0x%04x\n",
DRM_DEBUG("Unknown bits in load/store: 0x%04x\n",
surf->bits);
return -EINVAL;
}

if (tiling > VC4_TILING_FORMAT_LT) {
DRM_ERROR("Bad tiling format\n");
DRM_DEBUG("Bad tiling format\n");
return -EINVAL;
}

if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
if (format != 0) {
DRM_ERROR("No color format should be set for ZS\n");
DRM_DEBUG("No color format should be set for ZS\n");
return -EINVAL;
}
cpp = 4;
Expand All @@ -499,16 +499,16 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
cpp = 4;
break;
default:
DRM_ERROR("Bad tile buffer format\n");
DRM_DEBUG("Bad tile buffer format\n");
return -EINVAL;
}
} else {
DRM_ERROR("Bad load/store buffer %d.\n", buffer);
DRM_DEBUG("Bad load/store buffer %d.\n", buffer);
return -EINVAL;
}

if (surf->offset & 0xf) {
DRM_ERROR("load/store buffer must be 16b aligned.\n");
DRM_DEBUG("load/store buffer must be 16b aligned.\n");
return -EINVAL;
}

Expand All @@ -533,15 +533,15 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
int cpp;

if (surf->flags != 0) {
DRM_ERROR("No flags supported on render config.\n");
DRM_DEBUG("No flags supported on render config.\n");
return -EINVAL;
}

if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK |
VC4_RENDER_CONFIG_FORMAT_MASK |
VC4_RENDER_CONFIG_MS_MODE_4X |
VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
DRM_ERROR("Unknown bits in render config: 0x%04x\n",
DRM_DEBUG("Unknown bits in render config: 0x%04x\n",
surf->bits);
return -EINVAL;
}
Expand All @@ -556,7 +556,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;

if (tiling > VC4_TILING_FORMAT_LT) {
DRM_ERROR("Bad tiling format\n");
DRM_DEBUG("Bad tiling format\n");
return -EINVAL;
}

Expand All @@ -569,7 +569,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
cpp = 4;
break;
default:
DRM_ERROR("Bad tile buffer format\n");
DRM_DEBUG("Bad tile buffer format\n");
return -EINVAL;
}

Expand All @@ -590,7 +590,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)

if (args->min_x_tile > args->max_x_tile ||
args->min_y_tile > args->max_y_tile) {
DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n",
DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
args->min_x_tile, args->min_y_tile,
args->max_x_tile, args->max_y_tile);
return -EINVAL;
Expand All @@ -599,7 +599,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
if (has_bin &&
(args->max_x_tile > exec->bin_tiles_x ||
args->max_y_tile > exec->bin_tiles_y)) {
DRM_ERROR("Render tiles (%d,%d) outside of bin config "
DRM_DEBUG("Render tiles (%d,%d) outside of bin config "
"(%d,%d)\n",
args->max_x_tile, args->max_y_tile,
exec->bin_tiles_x, exec->bin_tiles_y);
Expand Down Expand Up @@ -642,7 +642,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
*/
if (!setup.color_write && !setup.zs_write &&
!setup.msaa_color_write && !setup.msaa_zs_write) {
DRM_ERROR("RCL requires color or Z/S write\n");
DRM_DEBUG("RCL requires color or Z/S write\n");
return -EINVAL;
}

Expand Down
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