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Merge branch 'yaml-bindings-for-v4.21' into dt/next
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@@ -15,6 +15,7 @@ | |
*.bin | ||
*.bz2 | ||
*.c.[012]*.* | ||
*.dt.yaml | ||
*.dtb | ||
*.dtb.S | ||
*.dwo | ||
|
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@@ -159,6 +159,7 @@ Peter Oruba <[email protected]> | |
Peter Oruba <[email protected]> | ||
Pratyush Anand <[email protected]> <[email protected]> | ||
Praveen BP <[email protected]> | ||
Punit Agrawal <[email protected]> <[email protected]> | ||
Qais Yousef <[email protected]> <[email protected]> | ||
Oleksij Rempel <[email protected]> <[email protected]> | ||
Oleksij Rempel <[email protected]> <[email protected]> | ||
|
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*.example.dts | ||
processed-schema.yaml |
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# SPDX-License-Identifier: GPL-2.0 | ||
DT_DOC_CHECKER ?= dt-doc-validate | ||
DT_EXTRACT_EX ?= dt-extract-example | ||
DT_MK_SCHEMA ?= dt-mk-schema | ||
DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u) | ||
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quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<) | ||
cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \ | ||
$(DT_EXTRACT_EX) $< > $@ | ||
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$(obj)/%.example.dts: $(src)/%.yaml FORCE | ||
$(call if_changed,chk_binding) | ||
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DT_TMP_SCHEMA := processed-schema.yaml | ||
extra-y += $(DT_TMP_SCHEMA) | ||
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quiet_cmd_mk_schema = SCHEMA $@ | ||
cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(filter-out FORCE, $^) | ||
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DT_DOCS = $(shell cd $(srctree)/$(src) && find * -name '*.yaml') | ||
DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) | ||
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extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) | ||
extra-y += $(patsubst $(src)/%.yaml,%.example.dtb, $(DT_SCHEMA_FILES)) | ||
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$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE | ||
$(call if_changed,mk_schema) |
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# SPDX-License-Identifier: GPL-2.0 | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/arm/altera.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Altera's SoCFPGA platform device tree bindings | ||
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maintainers: | ||
- Dinh Nguyen <[email protected]> | ||
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properties: | ||
compatible: | ||
items: | ||
- enum: | ||
- altr,socfpga-cyclone5 | ||
- altr,socfpga-arria5 | ||
- altr,socfpga-arria10 | ||
- const: altr,socfpga | ||
... |
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11
Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt
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Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
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# SPDX-License-Identifier: GPL-2.0 | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Altera SOCFPGA Clock Manager | ||
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maintainers: | ||
- Dinh Nguyen <[email protected]> | ||
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description: test | ||
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properties: | ||
compatible: | ||
items: | ||
- const: altr,clk-mgr | ||
reg: | ||
maxItems: 1 | ||
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required: | ||
- compatible | ||
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examples: | ||
- | | ||
clkmgr@ffd04000 { | ||
compatible = "altr,clk-mgr"; | ||
reg = <0xffd04000 0x1000>; | ||
}; | ||
... |
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/arm/calxeda.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Calxeda Platforms Device Tree Bindings | ||
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maintainers: | ||
- Rob Herring <[email protected]> | ||
description: |+ | ||
Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC | ||
or Cortex-A15 based ECX-2000 SOCs | ||
properties: | ||
$nodename: | ||
const: '/' | ||
compatible: | ||
items: | ||
- enum: | ||
- calxeda,highbank | ||
- calxeda,ecx-2000 |
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