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staging: wilc1000: remove unused code prior to throughput enhancement…
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… in SPI

The firmware now uses throughput enhancement code by default for SPI so
remove the previous implementation as its not used anymore. Removed the
use of 'has_thrpt_enh' element as its always true.

Signed-off-by: Ajay Singh <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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ajaykathat authored and gregkh committed Jan 22, 2020
1 parent 1d58fec commit b17028d
Showing 1 changed file with 4 additions and 139 deletions.
143 changes: 4 additions & 139 deletions drivers/staging/wilc1000/spi.c
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@
struct wilc_spi {
int crc_off;
int nint;
int has_thrpt_enh;
};

static const struct wilc_hif_func wilc_hif_spi;
Expand Down Expand Up @@ -897,163 +896,29 @@ static int wilc_spi_init(struct wilc *wilc, bool resume)
return 0;
}

spi_priv->has_thrpt_enh = 1;

isinit = 1;

return 1;
}

static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
{
struct spi_device *spi = to_spi_device(wilc->dev);
struct wilc_spi *spi_priv = wilc->bus_data;
int ret;

if (spi_priv->has_thrpt_enh) {
ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
size);
*size = *size & IRQ_DMA_WD_CNT_MASK;
} else {
u32 tmp;
u32 byte_cnt;

ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
&byte_cnt);
if (!ret) {
dev_err(&spi->dev,
"Failed read WILC_VMM_TO_HOST_SIZE ...\n");
return ret;
}
tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
*size = tmp;
}
ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, size);
*size = *size & IRQ_DMA_WD_CNT_MASK;

return ret;
}

static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
{
struct spi_device *spi = to_spi_device(wilc->dev);
struct wilc_spi *spi_priv = wilc->bus_data;
int ret;
u32 tmp;
u32 byte_cnt;
bool unexpected_irq;
int j;
u32 unknown_mask;
u32 irq_flags;
int k = IRG_FLAGS_OFFSET + 5;

if (spi_priv->has_thrpt_enh)
return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
int_status);
ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
if (!ret) {
dev_err(&spi->dev,
"Failed read WILC_VMM_TO_HOST_SIZE ...\n");
return ret;
}
tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;

j = 0;
do {
wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);

if (spi_priv->nint > 5) {
wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
tmp |= (((irq_flags >> 0) & 0x7) << k);
}

unknown_mask = ~((1ul << spi_priv->nint) - 1);

unexpected_irq = (tmp >> IRG_FLAGS_OFFSET) & unknown_mask;
if (unexpected_irq) {
dev_err(&spi->dev,
"Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
j, tmp, unknown_mask);
}

j++;
} while (unexpected_irq);

*int_status = tmp;

return ret;
return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, int_status);
}

static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
{
struct spi_device *spi = to_spi_device(wilc->dev);
struct wilc_spi *spi_priv = wilc->bus_data;
int ret;
u32 flags;
u32 tbl_ctl;

if (spi_priv->has_thrpt_enh) {
return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
val);
}

flags = val & (BIT(MAX_NUM_INT) - 1);
if (flags) {
int i;

ret = 1;
for (i = 0; i < spi_priv->nint; i++) {
/*
* No matter what you write 1 or 0,
* it will clear interrupt.
*/
if (flags & 1)
ret = wilc_spi_write_reg(wilc,
0x10c8 + i * 4, 1);
if (!ret)
break;
flags >>= 1;
}
if (!ret) {
dev_err(&spi->dev,
"Failed wilc_spi_write_reg, set reg %x ...\n",
0x10c8 + i * 4);
return ret;
}
for (i = spi_priv->nint; i < MAX_NUM_INT; i++) {
if (flags & 1)
dev_err(&spi->dev,
"Unexpected interrupt cleared %d...\n",
i);
flags >>= 1;
}
}

tbl_ctl = 0;
/* select VMM table 0 */
if (val & SEL_VMM_TBL0)
tbl_ctl |= BIT(0);
/* select VMM table 1 */
if (val & SEL_VMM_TBL1)
tbl_ctl |= BIT(1);

ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
if (!ret) {
dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
return ret;
}

if (val & EN_VMM) {
/*
* enable vmm transfer.
*/
ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
if (!ret) {
dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
return ret;
}
}

return ret;
return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE, val);
}

static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
Expand Down

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