Skip to content

Commit

Permalink
Merge tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kern…
Browse files Browse the repository at this point in the history 
…el/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:
 "Some things that I missed due to travel, or that came in late.

  Two fixes also going to stable:

   - A revert of a buggy change to the 8xx TLB miss handlers.

   - Our flushing of SPE (Signal Processing Engine) registers on fork
     was broken.

  Other changes:

   - A change to the KVM decrementer emulation to use proper APIs.

   - Some cleanups to the way we do code patching in the 8xx code.

   - Expose the maximum possible memory for the system in
     /proc/powerpc/lparcfg.

   - Merge some updates from Scott: "a couple device tree updates, and a
     fix for a missing prototype warning"

  A few other minor fixes and a handful of fixes for our selftests.

  Thanks to: Aravinda Prasad, Breno Leitao, Camelia Groza, Christophe
  Leroy, Felipe Rechia, Joel Stanley, Naveen N. Rao, Paul Mackerras,
  Scott Wood, Tyrel Datwyler"

* tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (21 commits)
  selftests/powerpc: Fix compilation issue due to asm label
  selftests/powerpc/cache_shape: Fix out-of-tree build
  selftests/powerpc/switch_endian: Fix out-of-tree build
  selftests/powerpc/pmu: Link ebb tests with -no-pie
  selftests/powerpc/signal: Fix out-of-tree build
  selftests/powerpc/ptrace: Fix out-of-tree build
  powerpc/xmon: Relax frame size for clang
  selftests: powerpc: Fix warning for security subdir
  selftests/powerpc: Relax L1d miss targets for rfi_flush test
  powerpc/process: Fix flush_all_to_thread for SPE
  powerpc/pseries: add missing cpumask.h include file
  selftests/powerpc: Fix ptrace tm failure
  KVM: PPC: Use exported tb_to_ns() function in decrementer emulation
  powerpc/pseries: Export maximum memory value
  powerpc/8xx: Use patch_site for perf counters setup
  powerpc/8xx: Use patch_site for memory setup patching
  powerpc/code-patching: Add a helper to get the address of a patch_site
  Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP"
  powerpc/8xx: add missing header in 8xx_mmu.c
  powerpc/8xx: Add DT node for using the SEC engine of the MPC885
  ...
  • Loading branch information
@torvalds
torvalds committed Nov 2, 2018
2 parents 63c6e18 + 1936f09 commit b69f9e1
Show file tree
Hide file tree
Showing 22 changed files with 169 additions and 145 deletions.
4 changes: 2 additions & 2 deletions arch/powerpc/boot/dts/fsl/t2080rdb.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -77,12 +77,12 @@
};

ethernet@f0000 {
phy-handle = <&xg_cs4315_phy1>;
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};

ethernet@f2000 {
phy-handle = <&xg_cs4315_phy2>;
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};

Expand Down
13 changes: 12 additions & 1 deletion arch/powerpc/boot/dts/mpc885ads.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xff000000 0x4000>;
ranges = <0x0 0xff000000 0x28000>;
bus-frequency = <0>;

// Temporary -- will go away once kernel uses ranges for get_immrbase().
Expand Down Expand Up @@ -224,6 +224,17 @@
#size-cells = <0>;
};
};

crypto@20000 {
compatible = "fsl,sec1.2", "fsl,sec1.0";
reg = <0x20000 0x8000>;
interrupts = <1 1>;
interrupt-parent = <&PIC>;
fsl,num-channels = <1>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x05000154>;
};
};

chosen {
Expand Down
5 changes: 5 additions & 0 deletions arch/powerpc/include/asm/code-patching.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,11 @@ int raw_patch_instruction(unsigned int *addr, unsigned int instr);
int patch_instruction_site(s32 *addr, unsigned int instr);
int patch_branch_site(s32 *site, unsigned long target, int flags);

static inline unsigned long patch_site_addr(s32 *site)
{
return (unsigned long)site + *site;
}

int instr_is_relative_branch(unsigned int instr);
int instr_is_relative_link_branch(unsigned int instr);
int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
Expand Down
43 changes: 15 additions & 28 deletions arch/powerpc/include/asm/mmu-8xx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,20 +34,12 @@
* respectively NA for All or X for Supervisor and no access for User.
* Then we use the APG to say whether accesses are according to Page rules or
* "all Supervisor" rules (Access to all)
* We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:
* When that bit is not set access is done iaw "all user"
* which means no access iaw page rules.
* Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED
* 0x => No access => 11 (all accesses performed as user iaw page definition)
* 10 => No user => 01 (all accesses performed according to page definition)
* 11 => User => 00 (all accesses performed as supervisor iaw page definition)
* Therefore, we define 2 APG groups. lsb is _PMD_USER
* 0 => No user => 01 (all accesses performed according to page definition)
* 1 => User => 00 (all accesses performed as supervisor iaw page definition)
* We define all 16 groups so that all other bits of APG can take any value
*/
#ifdef CONFIG_SWAP
#define MI_APG_INIT 0xf4f4f4f4
#else
#define MI_APG_INIT 0x44444444
#endif

/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MI_RPN is written, bits in
Expand Down Expand Up @@ -115,20 +107,12 @@
* Supervisor and no access for user and NA for ALL.
* Then we use the APG to say whether accesses are according to Page rules or
* "all Supervisor" rules (Access to all)
* We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:
* When that bit is not set access is done iaw "all user"
* which means no access iaw page rules.
* Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED
* 0x => No access => 11 (all accesses performed as user iaw page definition)
* 10 => No user => 01 (all accesses performed according to page definition)
* 11 => User => 00 (all accesses performed as supervisor iaw page definition)
* Therefore, we define 2 APG groups. lsb is _PMD_USER
* 0 => No user => 01 (all accesses performed according to page definition)
* 1 => User => 00 (all accesses performed as supervisor iaw page definition)
* We define all 16 groups so that all other bits of APG can take any value
*/
#ifdef CONFIG_SWAP
#define MD_APG_INIT 0xf4f4f4f4
#else
#define MD_APG_INIT 0x44444444
#endif

/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MD_RPN is written, bits in
Expand Down Expand Up @@ -180,12 +164,6 @@
*/
#define SPRN_M_TW 799

/* APGs */
#define M_APG0 0x00000000
#define M_APG1 0x00000020
#define M_APG2 0x00000040
#define M_APG3 0x00000060

#ifdef CONFIG_PPC_MM_SLICES
#include <asm/nohash/32/slice.h>
#define SLICE_ARRAY_SIZE (1 << (32 - SLICE_LOW_SHIFT - 1))
Expand Down Expand Up @@ -251,6 +229,15 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
BUG();
}

/* patch sites */
extern s32 patch__itlbmiss_linmem_top;
extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp;
extern s32 patch__fixupdar_linmem_top;

extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2;
extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3;
extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf;

#endif /* !__ASSEMBLY__ */

#if defined(CONFIG_PPC_4K_PAGES)
Expand Down
1 change: 1 addition & 0 deletions arch/powerpc/include/asm/rtas.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@
#include <linux/spinlock.h>
#include <asm/page.h>
#include <linux/time.h>
#include <linux/cpumask.h>

/*
* Definitions for talking to the RTAS on CHRP machines.
Expand Down
97 changes: 57 additions & 40 deletions arch/powerpc/kernel/head_8xx.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include <asm/asm-offsets.h>
#include <asm/ptrace.h>
#include <asm/export.h>
#include <asm/code-patching-asm.h>

#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
/* By simply checking Address >= 0x80000000, we know if its a kernel address */
Expand Down Expand Up @@ -318,8 +319,8 @@ InstructionTLBMiss:
cmpli cr0, r11, PAGE_OFFSET@h
#ifndef CONFIG_PIN_TLB_TEXT
/* It is assumed that kernel code fits into the first 8M page */
_ENTRY(ITLBMiss_cmp)
cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
0: cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
patch_site 0b, patch__itlbmiss_linmem_top
#endif
#endif
#endif
Expand Down Expand Up @@ -353,13 +354,14 @@ _ENTRY(ITLBMiss_cmp)
#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
mtcr r12
#endif

#ifdef CONFIG_SWAP
rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1
#endif
/* Load the MI_TWC with the attributes for this "segment." */
mtspr SPRN_MI_TWC, r11 /* Set segment attributes */

#ifdef CONFIG_SWAP
rlwinm r11, r10, 32-5, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
#endif
li r11, RPN_PATTERN | 0x200
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20 and 23 must be clear.
Expand All @@ -372,16 +374,17 @@ _ENTRY(ITLBMiss_cmp)
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */

/* Restore registers */
_ENTRY(itlb_miss_exit_1)
mfspr r10, SPRN_SPRG_SCRATCH0
0: mfspr r10, SPRN_SPRG_SCRATCH0
mfspr r11, SPRN_SPRG_SCRATCH1
#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
mfspr r12, SPRN_SPRG_SCRATCH2
#endif
rfi
patch_site 0b, patch__itlbmiss_exit_1

#ifdef CONFIG_PERF_EVENTS
_ENTRY(itlb_miss_perf)
lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
patch_site 0f, patch__itlbmiss_perf
0: lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
addi r11, r11, 1
stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
Expand Down Expand Up @@ -435,11 +438,11 @@ DataStoreTLBMiss:
#ifndef CONFIG_PIN_TLB_IMMR
cmpli cr0, r11, VIRT_IMMR_BASE@h
#endif
_ENTRY(DTLBMiss_cmp)
cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
patch_site 0b, patch__dtlbmiss_linmem_top
#ifndef CONFIG_PIN_TLB_IMMR
_ENTRY(DTLBMiss_jmp)
beq- DTLBMissIMMR
0: beq- DTLBMissIMMR
patch_site 0b, patch__dtlbmiss_immr_jmp
#endif
blt cr7, DTLBMissLinear
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
Expand Down Expand Up @@ -470,14 +473,22 @@ _ENTRY(DTLBMiss_jmp)
* above.
*/
rlwimi r11, r10, 0, _PAGE_GUARDED
#ifdef CONFIG_SWAP
/* _PAGE_ACCESSED has to be set. We use second APG bit for that, 0
* on that bit will represent a Non Access group
*/
rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1
#endif
mtspr SPRN_MD_TWC, r11

/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
* We also need to know if the insn is a load/store, so:
* Clear _PAGE_PRESENT and load that which will
* trap into DTLB Error with store bit set accordinly.
*/
/* PRESENT=0x1, ACCESSED=0x20
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
* r10 = (r10 & ~PRESENT) | r11;
*/
#ifdef CONFIG_SWAP
rlwinm r11, r10, 32-5, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
Expand All @@ -489,14 +500,16 @@ _ENTRY(DTLBMiss_jmp)

/* Restore registers */
mtspr SPRN_DAR, r11 /* Tag DAR */
_ENTRY(dtlb_miss_exit_1)
mfspr r10, SPRN_SPRG_SCRATCH0

0: mfspr r10, SPRN_SPRG_SCRATCH0
mfspr r11, SPRN_SPRG_SCRATCH1
mfspr r12, SPRN_SPRG_SCRATCH2
rfi
patch_site 0b, patch__dtlbmiss_exit_1

#ifdef CONFIG_PERF_EVENTS
_ENTRY(dtlb_miss_perf)
lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
patch_site 0f, patch__dtlbmiss_perf
0: lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
addi r11, r11, 1
stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
Expand Down Expand Up @@ -637,8 +650,8 @@ InstructionBreakpoint:
*/
DTLBMissIMMR:
mtcr r12
/* Set 512k byte guarded page and mark it valid and accessed */
li r10, MD_PS512K | MD_GUARDED | MD_SVALID | M_APG2
/* Set 512k byte guarded page and mark it valid */
li r10, MD_PS512K | MD_GUARDED | MD_SVALID
mtspr SPRN_MD_TWC, r10
mfspr r10, SPRN_IMMR /* Get current IMMR */
rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
Expand All @@ -648,16 +661,17 @@ DTLBMissIMMR:

li r11, RPN_PATTERN
mtspr SPRN_DAR, r11 /* Tag DAR */
_ENTRY(dtlb_miss_exit_2)
mfspr r10, SPRN_SPRG_SCRATCH0

0: mfspr r10, SPRN_SPRG_SCRATCH0
mfspr r11, SPRN_SPRG_SCRATCH1
mfspr r12, SPRN_SPRG_SCRATCH2
rfi
patch_site 0b, patch__dtlbmiss_exit_2

DTLBMissLinear:
mtcr r12
/* Set 8M byte page and mark it valid and accessed */
li r11, MD_PS8MEG | MD_SVALID | M_APG2
/* Set 8M byte page and mark it valid */
li r11, MD_PS8MEG | MD_SVALID
mtspr SPRN_MD_TWC, r11
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
Expand All @@ -666,28 +680,29 @@ DTLBMissLinear:

li r11, RPN_PATTERN
mtspr SPRN_DAR, r11 /* Tag DAR */
_ENTRY(dtlb_miss_exit_3)
mfspr r10, SPRN_SPRG_SCRATCH0

0: mfspr r10, SPRN_SPRG_SCRATCH0
mfspr r11, SPRN_SPRG_SCRATCH1
mfspr r12, SPRN_SPRG_SCRATCH2
rfi
patch_site 0b, patch__dtlbmiss_exit_3

#ifndef CONFIG_PIN_TLB_TEXT
ITLBMissLinear:
mtcr r12
/* Set 8M byte page and mark it valid,accessed */
li r11, MI_PS8MEG | MI_SVALID | M_APG2
/* Set 8M byte page and mark it valid */
li r11, MI_PS8MEG | MI_SVALID
mtspr SPRN_MI_TWC, r11
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
_PAGE_PRESENT
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */

_ENTRY(itlb_miss_exit_2)
mfspr r10, SPRN_SPRG_SCRATCH0
0: mfspr r10, SPRN_SPRG_SCRATCH0
mfspr r11, SPRN_SPRG_SCRATCH1
mfspr r12, SPRN_SPRG_SCRATCH2
rfi
patch_site 0b, patch__itlbmiss_exit_2
#endif

/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
Expand All @@ -705,8 +720,10 @@ FixupDAR:/* Entry point for dcbx workaround. */
mfspr r11, SPRN_M_TW /* Get level 1 table */
blt+ 3f
rlwinm r11, r10, 16, 0xfff8
_ENTRY(FixupDAR_cmp)
cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h

0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
patch_site 0b, patch__fixupdar_linmem_top

/* create physical page address from effective address */
tophys(r11, r10)
blt- cr7, 201f
Expand Down Expand Up @@ -960,7 +977,7 @@ initial_mmu:
ori r8, r8, MI_EVALID /* Mark it valid */
mtspr SPRN_MI_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID | M_APG2 /* Make it valid, APG 2 */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr SPRN_MI_TWC, r8
li r8, MI_BOOTINIT /* Create RPN for address 0 */
mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
Expand All @@ -987,7 +1004,7 @@ initial_mmu:
ori r8, r8, MD_EVALID /* Mark it valid */
mtspr SPRN_MD_EPN, r8
li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
ori r8, r8, MD_SVALID | M_APG2 /* Make it valid and accessed */
ori r8, r8, MD_SVALID /* Make it valid */
mtspr SPRN_MD_TWC, r8
mr r8, r9 /* Create paddr for TLB */
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
Expand Down
3 changes: 1 addition & 2 deletions arch/powerpc/kernel/process.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -590,12 +590,11 @@ void flush_all_to_thread(struct task_struct *tsk)
if (tsk->thread.regs) {
preempt_disable();
BUG_ON(tsk != current);
save_all(tsk);

#ifdef CONFIG_SPE
if (tsk->thread.regs->msr & MSR_SPE)
tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
#endif
save_all(tsk);

preempt_enable();
}
Expand Down
3 changes: 1 addition & 2 deletions arch/powerpc/kvm/book3s_hv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2337,8 +2337,7 @@ static void kvmppc_set_timer(struct kvm_vcpu *vcpu)
kvmppc_core_prepare_to_enter(vcpu);
return;
}
dec_nsec = (vcpu->arch.dec_expires - now) * NSEC_PER_SEC
/ tb_ticks_per_sec;
dec_nsec = tb_to_ns(vcpu->arch.dec_expires - now);
hrtimer_start(&vcpu->arch.dec_timer, dec_nsec, HRTIMER_MODE_REL);
vcpu->arch.timer_running = 1;
}
Expand Down
Loading

0 comments on commit b69f9e1

Please sign in to comment.