Adjust vertical retraces + SBB running fine

fpga/tn_vdp_v3_v9958/impl/gwsynthesis/tn_vdp_v3_v9958.log

@@ -27,13 +27,13 @@ Undeclared symbol 'rst_n', assumed default net type 'wire'("D:\src\tn_vdp\fpga\t
 Undeclared symbol 'clk_135', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":123)
 Undeclared symbol 'clk_sdram', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":138)
 Undeclared symbol 'clk_sdramp', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":140)
-Undeclared symbol 'cpuclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":342)
-Undeclared symbol 'clk_audio_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":407)
-Undeclared symbol 'sample_valid', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":511)
-WARN  (EX2830) : Data object 'clk_sck' is already declared("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":522)
-Previous declaration of 'clk_sck' is from here("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":519)
-WARN  (EX3671) : Second declaration of 'clk_sck' is ignored("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":522)
-Undeclared symbol 'sckclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":532)
+Undeclared symbol 'cpuclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":341)
+Undeclared symbol 'clk_audio_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":408)
+Undeclared symbol 'sample_valid', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":512)
+WARN  (EX2830) : Data object 'clk_sck' is already declared("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":523)
+Previous declaration of 'clk_sck' is from here("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":520)
+WARN  (EX3671) : Second declaration of 'clk_sck' is ignored("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":523)
+Undeclared symbol 'sckclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":533)
 Analyzing Verilog file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vram.v'
 Analyzing Verilog file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\pinfilter.v'
 Analyzing Verilog file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v'
@@ -111,12 +111,12 @@ Analyzing architecture 'rtl'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_wai
 Analyzing VHDL file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vencode.vhd'
 Analyzing entity 'vencode'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vencode.vhd":37)
 Analyzing architecture 'rtl'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vencode.vhd":57)
-WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":448)
-WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":474)
-WARN  (EX3073) : Port 'tmds_clock' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":485)
+WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":449)
+WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":475)
+WARN  (EX3073) : Port 'tmds_clock' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":486)
 Compiling module 'v9958_top'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":3)
-WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":516)
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":517)
+WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":518)
 Compiling module 'CLK_135'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\gowin\clk_135.v":10)
 Compiling module 'CLK_108P'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\gowin\clk_108p.v":10)
 WARN  (EX3073) : Port 'dout32' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\memory_controller.v":60)
@@ -199,7 +199,7 @@ Extracting RAM for identifier 'audio_sample_word_buffer'("D:\src\tn_vdp\fpga\tn_
 Compiling module 'auxiliary_video_information_info_frame(VIDEO_ID_CODE=32'sb00000000000000000000000000010001)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\auxiliary_video_information_info_frame.sv":5)
 WARN  (EX1998) : Net 'headers[255][23]' does not have a driver("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\packet_picker.sv":29)
 WARN  (EX1998) : Net 'subs[255][3][55]' does not have a driver("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\packet_picker.sv":30)
-WARN  (EX3670) : Actual bit length 10 differs from formal bit length 12 for port 'cx'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":471)
+WARN  (EX3670) : Actual bit length 10 differs from formal bit length 12 for port 'cx'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":472)
 Compiling module 'serializer(VIDEO_RATE=0)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\serializer.sv":3)
 Compiling module 'SPI_MCP3202'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\SPI_MCP3202.v":20)
 WARN  (EX3791) : Expression size 13 truncated to fit in target size 12("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\SPI_MCP3202.v":63)
@@ -208,16 +208,14 @@ WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\t
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":13)
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":15)
 WARN  (EX3791) : Expression size 10 truncated to fit in target size 9("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":34)
-Switching to VHDL mode to elaborate design unit 'LPF1'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":557)
+Switching to VHDL mode to elaborate design unit 'LPF1'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":558)
 Processing 'LPF1(msbi=32)(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\lpf.vhd":39)
-WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'IDATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":555)
-WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'ODATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":556)
-Returning to Verilog mode to proceed with elaboration("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":557)
+WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'IDATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":556)
+WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'ODATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":557)
+Returning to Verilog mode to proceed with elaboration("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":558)
 NOTE  (EX0101) : Current top module is "v9958_top"
-WARN  (EX0211) : The output port "gromclk" of module "v9958_top" has no driver, assigning undriven bits to Z, simulation mismatch possible("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":17)
 [5%] Running netlist conversion ...
 WARN  (CV0016) : Input clk_50 is unused("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":5)
-WARN  (CV0016) : Input gromclk_ena_n is unused("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":31)
 Running device independent optimization ...
 [10%] Optimizing Phase 0 completed
 [15%] Optimizing Phase 1 completed