stability fixres plus interrupt

lfantoniosi · Jul 20, 2023 · c32f2ad · c32f2ad
1 parent c662fef
commit c32f2ad
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Showing 21 changed files with 40,698 additions and 39,661 deletions.
diff --git a/fpga/tn_vdp_v3_v9958/impl/gwsynthesis/tn_vdp_v3_v9958.log b/fpga/tn_vdp_v3_v9958/impl/gwsynthesis/tn_vdp_v3_v9958.log
@@ -27,14 +27,14 @@ Undeclared symbol 'rst_n', assumed default net type 'wire'("D:\src\tn_vdp\fpga\t
 Undeclared symbol 'clk_135', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":123)
 Undeclared symbol 'clk_sdram', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":138)
 Undeclared symbol 'clk_sdramp', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":140)
-Undeclared symbol 'cpuclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":355)
-Undeclared symbol 'gromclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":369)
-Undeclared symbol 'clk_audio_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":418)
-Undeclared symbol 'sample_valid', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":522)
-WARN  (EX2830) : Data object 'clk_sck' is already declared("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":533)
-Previous declaration of 'clk_sck' is from here("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":530)
-WARN  (EX3671) : Second declaration of 'clk_sck' is ignored("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":533)
-Undeclared symbol 'sckclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":542)
+Undeclared symbol 'cpuclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":341)
+Undeclared symbol 'gromclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":355)
+Undeclared symbol 'clk_audio_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":404)
+Undeclared symbol 'sample_valid', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":508)
+WARN  (EX2830) : Data object 'clk_sck' is already declared("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":519)
+Previous declaration of 'clk_sck' is from here("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":516)
+WARN  (EX3671) : Second declaration of 'clk_sck' is ignored("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":519)
+Undeclared symbol 'sckclk_w', assumed default net type 'wire'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":528)
 Analyzing Verilog file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vram.v'
 Analyzing Verilog file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\pinfilter.v'
 Analyzing Verilog file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v'
@@ -112,12 +112,12 @@ Analyzing architecture 'rtl'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_wai
 Analyzing VHDL file 'D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vencode.vhd'
 Analyzing entity 'vencode'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vencode.vhd":37)
 Analyzing architecture 'rtl'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vencode.vhd":57)
-WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":459)
-WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":485)
-WARN  (EX3073) : Port 'tmds_clock' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":496)
+WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":445)
+WARN  (EX3073) : Port 'frame_width' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":471)
+WARN  (EX3073) : Port 'tmds_clock' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":482)
 Compiling module 'v9958_top'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":3)
-WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":527)
-WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":528)
+WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":513)
+WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":514)
 Compiling module 'CLK_135'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\gowin\clk_135.v":10)
 Compiling module 'CLK_108P'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\gowin\clk_108p.v":10)
 WARN  (EX3073) : Port 'dout32' remains unconnected for this instance("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\memory_controller.v":60)
@@ -127,7 +127,7 @@ WARN  (EX3791) : Expression size 16 truncated to fit in target size 15("D:\src\t
 WARN  (EX3791) : Expression size 21 truncated to fit in target size 20("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\memory_controller.v":86)
 WARN  (EX3670) : Actual bit length 21 differs from formal bit length 22 for port 'addr'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":169)
 Compiling module 'PINFILTER'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\pinfilter.v":1)
-Switching to VHDL mode to elaborate design unit 'VDP'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":327)
+Switching to VHDL mode to elaborate design unit 'VDP'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":313)
 Processing 'VDP(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp.vhd":254)
 Processing 'VDP_NTSC_PAL(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_ntsc_pal.vhd":96)
 Processing 'VDP_VGA(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_vga.vhd":102)
@@ -165,7 +165,7 @@ Extracting RAM for identifier 'blkram'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\r
 Processing 'VDP_COMMAND(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_command.vhd":67)
 WARN  (EX4160) : Latch inferred for net 'NXCOUNT[9]'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_command.vhd":783)
 Processing 'VDP_WAIT_CONTROL(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\vdp\vdp_wait_control.vhd":59)
-Returning to Verilog mode to proceed with elaboration("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":327)
+Returning to Verilog mode to proceed with elaboration("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":313)
 Compiling module 'CLOCK_DIV(CLK_SRC=125.0,CLK_DIV=3.58)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":1)
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":11)
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":12)
@@ -200,19 +200,19 @@ Extracting RAM for identifier 'audio_sample_word_buffer'("D:\src\tn_vdp\fpga\tn_
 Compiling module 'auxiliary_video_information_info_frame(VIDEO_ID_CODE=32'sb00000000000000000000000000010001)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\auxiliary_video_information_info_frame.sv":5)
 WARN  (EX1998) : Net 'headers[255][23]' does not have a driver("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\packet_picker.sv":29)
 WARN  (EX1998) : Net 'subs[255][3][55]' does not have a driver("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\packet_picker.sv":30)
-WARN  (EX3670) : Actual bit length 10 differs from formal bit length 12 for port 'cx'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":482)
+WARN  (EX3670) : Actual bit length 10 differs from formal bit length 12 for port 'cx'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":468)
 Compiling module 'serializer(VIDEO_RATE=0)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\hdmi\serializer.sv":3)
 Compiling module 'SPI_MCP3202'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\SPI_MCP3202.v":20)
 WARN  (EX3791) : Expression size 13 truncated to fit in target size 12("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\SPI_MCP3202.v":63)
 Compiling module 'CLOCK_DIV(CLK_DIV=0.9)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":1)
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":11)
 WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":12)
 WARN  (EX3791) : Expression size 10 truncated to fit in target size 9("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\clockdiv.v":22)
-Switching to VHDL mode to elaborate design unit 'LPF1'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":567)
+Switching to VHDL mode to elaborate design unit 'LPF1'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":553)
 Processing 'LPF1(msbi=32)(RTL)'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\lpf.vhd":39)
-WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'IDATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":565)
-WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'ODATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":566)
-Returning to Verilog mode to proceed with elaboration("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":567)
+WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'IDATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":551)
+WARN  (EX3670) : Actual bit length 32 differs from formal bit length 33 for port 'ODATA'("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":552)
+Returning to Verilog mode to proceed with elaboration("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":553)
 NOTE  (EX0101) : Current top module is "v9958_top"
 [5%] Running netlist conversion ...
 WARN  (CV0016) : Input clk_50 is unused("D:\src\tn_vdp\fpga\tn_vdp_v3_v9958\src\v9958_top.v":5)