arch/quark_se_c1000_ss: Switch to SPI DW driver

As QMSI driver does not support new SPI API. Signed-off-by: Tomasz Bursztyka <[email protected]>
liguoqing6 · Apr 4, 2018 · 4652f59 · 4652f59
1 parent dc49d0f
commit 4652f59
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Showing 2 changed files with 62 additions and 37 deletions.
diff --git a/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig b/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
@@ -218,54 +218,60 @@ endif # UART_QMSI
 
 if SPI
 
-config SPI_QMSI
-	def_bool n
-
-if SPI_QMSI
-config SPI_0
+config SPI_DW
 	def_bool y
 
-config SPI_0_NAME
-	default "SPI_2"
+if SPI_DW
 
-config SPI_0_IRQ_PRI
-	default 1
+config SPI_DW_FIFO_DEPTH
+	default 7
 
-config SPI_1
+config CLOCK_CONTROL
 	def_bool y
 
-config SPI_1_NAME
-	default "SPI_3"
-
-config SPI_1_IRQ_PRI
-	default 1
+config CLOCK_CONTROL_QUARK_SE
+	def_bool y
 
-endif
+config CLOCK_CONTROL_QUARK_SE_SENSOR
+	def_bool y
 
-config SPI_QMSI_SS
+config SPI_0
 	def_bool y
 
-if SPI_QMSI_SS
-config SPI_SS_0
+config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
+	def_bool n
+
+config SPI_DW_PORT_0_CLOCK_GATE
 	def_bool y
 
-config SPI_SS_0_NAME
-	default "SPI_0"
+config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME
+	default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
+
+config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
+	default 3
 
-config SPI_SS_0_IRQ_PRI
+config SPI_0_IRQ_PRI
 	default 1
 
-config SPI_SS_1
+config SPI_1
 	def_bool y
 
-config SPI_SS_1_NAME
-	default "SPI_1"
+config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
+	def_bool n
 
-config SPI_SS_1_IRQ_PRI
-	default 1
+config SPI_DW_PORT_1_CLOCK_GATE
+	def_bool y
 
-endif
+config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME
+	default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
+
+config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
+	default 4
+
+config SPI_1_IRQ_PRI
+	default 1
 
+endif # SPI_DW
 endif # SPI
 
 if AIO_COMPARATOR

diff --git a/arch/arc/soc/quark_se_c1000_ss/soc.h b/arch/arc/soc/quark_se_c1000_ss/soc.h
@@ -175,18 +175,37 @@
  * SPI
  */
 
-#define SPI_DW_PORT_0_REGS				0x80010000
-#define SPI_DW_PORT_1_REGS				0x80010100
+#ifdef CONFIG_SPI_DW
 
-#define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
-#define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
-#define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
+#define SPI_DW_PORT_0_REGS			0x80010000
+#define SPI_DW_PORT_1_REGS			0x80010100
 
-#define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
-#define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
-#define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
+#define SPI_DW_PORT_0_ERROR_INT_MASK		(SCSS_REGISTER_BASE + 0x430)
+#define SPI_DW_PORT_0_RX_INT_MASK		(SCSS_REGISTER_BASE + 0x434)
+#define SPI_DW_PORT_0_TX_INT_MASK		(SCSS_REGISTER_BASE + 0x438)
 
-#define SPI_DW_IRQ_FLAGS				0
+#define SPI_DW_PORT_1_ERROR_INT_MASK		(SCSS_REGISTER_BASE + 0x43C)
+#define SPI_DW_PORT_1_RX_INT_MASK		(SCSS_REGISTER_BASE + 0x440)
+#define SPI_DW_PORT_1_TX_INT_MASK		(SCSS_REGISTER_BASE + 0x444)
+
+#define SPI_DW_IRQ_FLAGS			0
+
+#define SPI_DW_PORT_2_REGS			0xB0001000
+#define SPI_DW_PORT_2_IRQ			IRQ_SPI_MST0_INTR
+#define SPI_DW_PORT_2_INT_MASK			(SCSS_REGISTER_BASE + 0x454)
+
+#define SPI_DW_PORT_3_REGS			0xB0001400
+#define SPI_DW_PORT_3_IRQ			IRQ_SPI_MST1_INTR
+#define SPI_DW_PORT_3_INT_MASK			(SCSS_REGISTER_BASE + 0x458)
+
+#endif /* CONFIG_SPI_DW */
+
+/* Clock */
+#define CLOCK_PERIPHERAL_BASE_ADDR		(SCSS_REGISTER_BASE + 0x18)
+#define CLOCK_EXTERNAL_BASE_ADDR		(SCSS_REGISTER_BASE + 0x24)
+#define CLOCK_SENSOR_BASE_ADDR			(SCSS_REGISTER_BASE + 0x28)
+#define CLOCK_SYSTEM_CLOCK_CONTROL		(SCSS_REGISTER_BASE + \
+						 SCSS_CCU_SYS_CLK_CTL)
 
 static inline void _quark_se_ss_ready(void)
 {