Generic HDL components to be used in different projects
Binary coded decimal to binary and vice versa converter.
Start conversion by asserting conv for 1 tick
Debounce signals from mechanical input devices (buttons, encoders, switches, etc)
Processes input from quadrature encoders. Generates clockwise and counterclockwise signals
- debouncer.sv
Single- and dual clock FIFOs. Two versions for each with or without interface
- ram.sv
I2C master with read and write functions
Iterative integer divider
Allows multiple RAM access without collision. Buffers requests for write and read and replies with read result
Quadrature LUT-based NCO
Convert a vector with multiple bits set to a vector with only one bit set (MSB or LSB)
Single- and dual port RAM
Recursive summation module
Shift-add multiplier
Stretches a pulse by specified amount. Delay is constant in respect to pulse centers