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CodeGen: Use MachineInstr& in RegisterCoalescer, NFC
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Remove a few more implicit iterator to pointer conversions by preferring
MachineInstr&.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274363 91177308-0d34-0410-b5e6-96231b3b80d8
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@dexonsmith
dexonsmith committed Jul 1, 2016
1 parent b9e2bc1 commit 7aad63c
Showing 1 changed file with 37 additions and 38 deletions.
75 changes: 37 additions & 38 deletions lib/CodeGen/RegisterCoalescer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -954,8 +954,8 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
MachineBasicBlock::iterator MII =
std::next(MachineBasicBlock::iterator(CopyMI));
TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
MachineInstr *NewMI = std::prev(MII);
NewMI->setDebugLoc(DL);
MachineInstr &NewMI = *std::prev(MII);
NewMI.setDebugLoc(DL);

// In a situation like the following:
// %vreg0:subreg = instr ; DefMI, subreg = DstIdx
Expand All @@ -964,7 +964,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
// %vreg1 = instr
const TargetRegisterClass *NewRC = CP.getNewRC();
if (DstIdx != 0) {
MachineOperand &DefMO = NewMI->getOperand(0);
MachineOperand &DefMO = NewMI.getOperand(0);
if (DefMO.getSubReg() == DstIdx) {
assert(SrcIdx == 0 && CP.isFlipped()
&& "Shouldn't have SrcIdx+DstIdx at this point");
Expand Down Expand Up @@ -996,17 +996,18 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
}
}

LIS->ReplaceMachineInstrInMaps(*CopyMI, *NewMI);
LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI);
CopyMI->eraseFromParent();
ErasedInstrs.insert(CopyMI);

// NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
// We need to remember these so we can add intervals once we insert
// NewMI into SlotIndexes.
SmallVector<unsigned, 4> NewMIImplDefs;
for (unsigned i = NewMI->getDesc().getNumOperands(),
e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
for (unsigned i = NewMI.getDesc().getNumOperands(),
e = NewMI.getNumOperands();
i != e; ++i) {
MachineOperand &MO = NewMI.getOperand(i);
if (MO.isReg() && MO.isDef()) {
assert(MO.isImplicit() && MO.isDead() &&
TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
Expand All @@ -1015,7 +1016,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
}

if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
unsigned NewIdx = NewMI->getOperand(0).getSubReg();
unsigned NewIdx = NewMI.getOperand(0).getSubReg();

if (DefRC != nullptr) {
if (NewIdx)
Expand All @@ -1033,7 +1034,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,

// Update machine operands and add flags.
updateRegDefsUses(DstReg, DstReg, DstIdx);
NewMI->getOperand(0).setSubReg(NewIdx);
NewMI.getOperand(0).setSubReg(NewIdx);
// Add dead subregister definitions if we are defining the whole register
// but only part of it is live.
// This could happen if the rematerialization instruction is rematerializing
Expand All @@ -1049,8 +1050,9 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
// at this point for the part that wasn't defined before we could have
// subranges missing the definition.
if (NewIdx == 0 && DstInt.hasSubRanges()) {
SlotIndex CurrIdx = LIS->getInstructionIndex(*NewMI);
SlotIndex DefIndex = CurrIdx.getRegSlot(NewMI->getOperand(0).isEarlyClobber());
SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
SlotIndex DefIndex =
CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
for (LiveInterval::SubRange &SR : DstInt.subranges()) {
Expand All @@ -1063,16 +1065,14 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
SR->createDeadDef(DefIndex, Alloc);
}
}
} else if (NewMI->getOperand(0).getReg() != CopyDstReg) {
} else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
// The New instruction may be defining a sub-register of what's actually
// been asked for. If so it must implicitly define the whole thing.
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Only expect virtual or physical registers in remat");
NewMI->getOperand(0).setIsDead(true);
NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
true /*IsDef*/,
true /*IsImp*/,
false /*IsKill*/));
NewMI.getOperand(0).setIsDead(true);
NewMI.addOperand(MachineOperand::CreateReg(
CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
// Record small dead def live-ranges for all the subregisters
// of the destination register.
// Otherwise, variables that live through may miss some
Expand All @@ -1089,29 +1089,29 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
// vreg1 will see the inteferences with CL but not with CH since
// no live-ranges would have been created for ECX.
// Fix that!
SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
for (MCRegUnitIterator Units(NewMI->getOperand(0).getReg(), TRI);
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
Units.isValid(); ++Units)
if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
}

if (NewMI->getOperand(0).getSubReg())
NewMI->getOperand(0).setIsUndef();
if (NewMI.getOperand(0).getSubReg())
NewMI.getOperand(0).setIsUndef();

// Transfer over implicit operands to the rematerialized instruction.
for (MachineOperand &MO : ImplicitOps)
NewMI->addOperand(MO);
NewMI.addOperand(MO);

SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
unsigned Reg = NewMIImplDefs[i];
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
}

DEBUG(dbgs() << "Remat: " << *NewMI);
DEBUG(dbgs() << "Remat: " << NewMI);
++NumReMats;

// The source interval can become smaller because we removed a use.
Expand Down Expand Up @@ -1849,7 +1849,7 @@ class JoinVals {

/// Return true if MI uses any of the given Lanes from Reg.
/// This does not include partial redefinitions of Reg.
bool usesLanes(const MachineInstr *MI, unsigned, unsigned, LaneBitmask) const;
bool usesLanes(const MachineInstr &MI, unsigned, unsigned, LaneBitmask) const;

/// Determine if ValNo is a copy of a value number in LR or Other.LR that will
/// be pruned:
Expand Down Expand Up @@ -2293,11 +2293,11 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
return true;
}

bool JoinVals::usesLanes(const MachineInstr *MI, unsigned Reg, unsigned SubIdx,
bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
LaneBitmask Lanes) const {
if (MI->isDebugValue())
if (MI.isDebugValue())
return false;
for (const MachineOperand &MO : MI->operands()) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
continue;
if (!MO.readsReg())
Expand Down Expand Up @@ -2352,7 +2352,7 @@ bool JoinVals::resolveConflicts(JoinVals &Other) {
unsigned TaintNum = 0;
for(;;) {
assert(MI != MBB->end() && "Bad LastMI");
if (usesLanes(MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
if (usesLanes(*MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
return false;
}
Expand Down Expand Up @@ -2912,16 +2912,15 @@ RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
}
else {
SmallVector<MachineInstr*, 2> Terminals;
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E; ++MII)
if (MII->isCopyLike()) {
if (applyTerminalRule(*MII))
Terminals.push_back(&(*MII));
for (MachineInstr &MII : *MBB)
if (MII.isCopyLike()) {
if (applyTerminalRule(MII))
Terminals.push_back(&MII);
else
WorkList.push_back(MII);
}
// Append the copies evicted by the terminal rule at the end of the list.
WorkList.append(Terminals.begin(), Terminals.end());
WorkList.push_back(&MII);
}
// Append the copies evicted by the terminal rule at the end of the list.
WorkList.append(Terminals.begin(), Terminals.end());
}
// Try coalescing the collected copies immediately, and remove the nulls.
// This prevents the WorkList from getting too large since most copies are
Expand Down

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