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AMDGPU: Remove implicit iterator conversions, NFC
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Remove remaining implicit conversions from MachineInstrBundleIterator to
MachineInstr* from the AMDGPU backend.  In most cases, I made them less
attractive by preferring MachineInstr& or using a ranged-based for loop.

Once all the backends are fixed I'll make the operator explicit so that
this doesn't bitrot back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274906 91177308-0d34-0410-b5e6-96231b3b80d8
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@dexonsmith
dexonsmith committed Jul 8, 2016
1 parent a5b3bc1 commit 83b2ab7
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Showing 9 changed files with 176 additions and 172 deletions.
9 changes: 3 additions & 6 deletions lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -660,11 +660,8 @@ MachineBasicBlock *AMDGPUCFGStructurizer::clone(MachineBasicBlock *MBB) {
MachineFunction *Func = MBB->getParent();
MachineBasicBlock *NewMBB = Func->CreateMachineBasicBlock();
Func->push_back(NewMBB); //insert to function
for (MachineBasicBlock::iterator It = MBB->begin(), E = MBB->end();
It != E; ++It) {
MachineInstr *MI = Func->CloneMachineInstr(It);
NewMBB->push_back(MI);
}
for (const MachineInstr &It : *MBB)
NewMBB->push_back(Func->CloneMachineInstr(&It));
return NewMBB;
}

Expand All @@ -690,7 +687,7 @@ void AMDGPUCFGStructurizer::wrapup(MachineBasicBlock *MBB) {
while (It != E) {
if (Pre->getOpcode() == AMDGPU::CONTINUE
&& It->getOpcode() == AMDGPU::ENDLOOP)
ContInstr.push_back(Pre);
ContInstr.push_back(&*Pre);
Pre = It;
++It;
}
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116 changes: 59 additions & 57 deletions lib/Target/AMDGPU/R600ClauseMergePass.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,8 @@ using namespace llvm;

namespace {

static bool isCFAlu(const MachineInstr *MI) {
switch (MI->getOpcode()) {
static bool isCFAlu(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case AMDGPU::CF_ALU:
case AMDGPU::CF_ALU_PUSH_BEFORE:
return true;
Expand All @@ -47,19 +47,19 @@ class R600ClauseMergePass : public MachineFunctionPass {
static char ID;
const R600InstrInfo *TII;

unsigned getCFAluSize(const MachineInstr *MI) const;
bool isCFAluEnabled(const MachineInstr *MI) const;
unsigned getCFAluSize(const MachineInstr &MI) const;
bool isCFAluEnabled(const MachineInstr &MI) const;

/// IfCvt pass can generate "disabled" ALU clause marker that need to be
/// removed and their content affected to the previous alu clause.
/// This function parse instructions after CFAlu until it find a disabled
/// CFAlu and merge the content, or an enabled CFAlu.
void cleanPotentialDisabledCFAlu(MachineInstr *CFAlu) const;
void cleanPotentialDisabledCFAlu(MachineInstr &CFAlu) const;

/// Check whether LatrCFAlu can be merged into RootCFAlu and do it if
/// it is the case.
bool mergeIfPossible(MachineInstr *RootCFAlu, const MachineInstr *LatrCFAlu)
const;
bool mergeIfPossible(MachineInstr &RootCFAlu,
const MachineInstr &LatrCFAlu) const;

public:
R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { }
Expand All @@ -71,38 +71,40 @@ class R600ClauseMergePass : public MachineFunctionPass {

char R600ClauseMergePass::ID = 0;

unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr *MI) const {
unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr &MI) const {
assert(isCFAlu(MI));
return MI->getOperand(
TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm();
return MI
.getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT))
.getImm();
}

bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr *MI) const {
bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr &MI) const {
assert(isCFAlu(MI));
return MI->getOperand(
TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm();
return MI
.getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled))
.getImm();
}

void R600ClauseMergePass::cleanPotentialDisabledCFAlu(MachineInstr *CFAlu)
const {
void R600ClauseMergePass::cleanPotentialDisabledCFAlu(
MachineInstr &CFAlu) const {
int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
MachineBasicBlock::iterator I = CFAlu, E = CFAlu->getParent()->end();
MachineBasicBlock::iterator I = CFAlu, E = CFAlu.getParent()->end();
I++;
do {
while (I!= E && !isCFAlu(I))
while (I != E && !isCFAlu(*I))
I++;
if (I == E)
return;
MachineInstr *MI = I++;
MachineInstr &MI = *I++;
if (isCFAluEnabled(MI))
break;
CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
MI->eraseFromParent();
CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
MI.eraseFromParent();
} while (I != E);
}

bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu,
const MachineInstr *LatrCFAlu) const {
bool R600ClauseMergePass::mergeIfPossible(MachineInstr &RootCFAlu,
const MachineInstr &LatrCFAlu) const {
assert(isCFAlu(RootCFAlu) && isCFAlu(LatrCFAlu));
int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
unsigned RootInstCount = getCFAluSize(RootCFAlu),
Expand All @@ -112,7 +114,7 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu,
DEBUG(dbgs() << "Excess inst counts\n");
return false;
}
if (RootCFAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
if (RootCFAlu.getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
return false;
// Is KCache Bank 0 compatible ?
int Mode0Idx =
Expand All @@ -121,12 +123,12 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu,
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
int KBank0LineIdx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
if (LatrCFAlu->getOperand(Mode0Idx).getImm() &&
RootCFAlu->getOperand(Mode0Idx).getImm() &&
(LatrCFAlu->getOperand(KBank0Idx).getImm() !=
RootCFAlu->getOperand(KBank0Idx).getImm() ||
LatrCFAlu->getOperand(KBank0LineIdx).getImm() !=
RootCFAlu->getOperand(KBank0LineIdx).getImm())) {
if (LatrCFAlu.getOperand(Mode0Idx).getImm() &&
RootCFAlu.getOperand(Mode0Idx).getImm() &&
(LatrCFAlu.getOperand(KBank0Idx).getImm() !=
RootCFAlu.getOperand(KBank0Idx).getImm() ||
LatrCFAlu.getOperand(KBank0LineIdx).getImm() !=
RootCFAlu.getOperand(KBank0LineIdx).getImm())) {
DEBUG(dbgs() << "Wrong KC0\n");
return false;
}
Expand All @@ -137,33 +139,33 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu,
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1);
int KBank1LineIdx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1);
if (LatrCFAlu->getOperand(Mode1Idx).getImm() &&
RootCFAlu->getOperand(Mode1Idx).getImm() &&
(LatrCFAlu->getOperand(KBank1Idx).getImm() !=
RootCFAlu->getOperand(KBank1Idx).getImm() ||
LatrCFAlu->getOperand(KBank1LineIdx).getImm() !=
RootCFAlu->getOperand(KBank1LineIdx).getImm())) {
if (LatrCFAlu.getOperand(Mode1Idx).getImm() &&
RootCFAlu.getOperand(Mode1Idx).getImm() &&
(LatrCFAlu.getOperand(KBank1Idx).getImm() !=
RootCFAlu.getOperand(KBank1Idx).getImm() ||
LatrCFAlu.getOperand(KBank1LineIdx).getImm() !=
RootCFAlu.getOperand(KBank1LineIdx).getImm())) {
DEBUG(dbgs() << "Wrong KC0\n");
return false;
}
if (LatrCFAlu->getOperand(Mode0Idx).getImm()) {
RootCFAlu->getOperand(Mode0Idx).setImm(
LatrCFAlu->getOperand(Mode0Idx).getImm());
RootCFAlu->getOperand(KBank0Idx).setImm(
LatrCFAlu->getOperand(KBank0Idx).getImm());
RootCFAlu->getOperand(KBank0LineIdx).setImm(
LatrCFAlu->getOperand(KBank0LineIdx).getImm());
if (LatrCFAlu.getOperand(Mode0Idx).getImm()) {
RootCFAlu.getOperand(Mode0Idx).setImm(
LatrCFAlu.getOperand(Mode0Idx).getImm());
RootCFAlu.getOperand(KBank0Idx).setImm(
LatrCFAlu.getOperand(KBank0Idx).getImm());
RootCFAlu.getOperand(KBank0LineIdx)
.setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm());
}
if (LatrCFAlu->getOperand(Mode1Idx).getImm()) {
RootCFAlu->getOperand(Mode1Idx).setImm(
LatrCFAlu->getOperand(Mode1Idx).getImm());
RootCFAlu->getOperand(KBank1Idx).setImm(
LatrCFAlu->getOperand(KBank1Idx).getImm());
RootCFAlu->getOperand(KBank1LineIdx).setImm(
LatrCFAlu->getOperand(KBank1LineIdx).getImm());
if (LatrCFAlu.getOperand(Mode1Idx).getImm()) {
RootCFAlu.getOperand(Mode1Idx).setImm(
LatrCFAlu.getOperand(Mode1Idx).getImm());
RootCFAlu.getOperand(KBank1Idx).setImm(
LatrCFAlu.getOperand(KBank1Idx).getImm());
RootCFAlu.getOperand(KBank1LineIdx)
.setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm());
}
RootCFAlu->getOperand(CntIdx).setImm(CumuledInsts);
RootCFAlu->setDesc(TII->get(LatrCFAlu->getOpcode()));
RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts);
RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode()));
return true;
}

Expand All @@ -180,18 +182,18 @@ bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
MachineBasicBlock::iterator LatestCFAlu = E;
while (I != E) {
MachineInstr *MI = I++;
if ((!TII->canBeConsideredALU(*MI) && !isCFAlu(MI)) ||
TII->mustBeLastInClause(MI->getOpcode()))
MachineInstr &MI = *I++;
if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) ||
TII->mustBeLastInClause(MI.getOpcode()))
LatestCFAlu = E;
if (!isCFAlu(MI))
continue;
cleanPotentialDisabledCFAlu(MI);

if (LatestCFAlu != E && mergeIfPossible(LatestCFAlu, MI)) {
MI->eraseFromParent();
if (LatestCFAlu != E && mergeIfPossible(*LatestCFAlu, MI)) {
MI.eraseFromParent();
} else {
assert(MI->getOperand(8).getImm() && "CF ALU instruction disabled");
assert(MI.getOperand(8).getImm() && "CF ALU instruction disabled");
LatestCFAlu = MI;
}
}
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