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[PowerPC] Remove need for adjustFixupOffst hack
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Now that applyFixup understands differently-sized fixups, we can define
fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte
fixups, applied at an offset of 2 relative to the start of the 
instruction text.

This has the benefit that if we actually need to generate a real
relocation record, its address will come out correctly automatically,
without having to fiddle with the offset in adjustFixupOffset.

Tested on both 64-bit and 32-bit PowerPC, using external and
integrated assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
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@uweigand
uweigand committed May 15, 2013
1 parent ddbf053 commit 9122396
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Showing 4 changed files with 52 additions and 66 deletions.
12 changes: 6 additions & 6 deletions lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -57,13 +57,13 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case FK_Data_1:
return 1;
case FK_Data_2:
case PPC::fixup_ppc_ha16:
case PPC::fixup_ppc_lo16:
case PPC::fixup_ppc_lo16_ds:
return 2;
case FK_Data_4:
case PPC::fixup_ppc_brcond14:
case PPC::fixup_ppc_br24:
case PPC::fixup_ppc_ha16:
case PPC::fixup_ppc_lo16:
case PPC::fixup_ppc_lo16_ds:
return 4;
case FK_Data_8:
return 8;
Expand Down Expand Up @@ -100,9 +100,9 @@ const Target &TheTarget;
// name offset bits flags
{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_ppc_lo16", 16, 16, 0 },
{ "fixup_ppc_ha16", 16, 16, 0 },
{ "fixup_ppc_lo16_ds", 16, 14, 0 },
{ "fixup_ppc_lo16", 0, 16, 0 },
{ "fixup_ppc_ha16", 0, 16, 0 },
{ "fixup_ppc_lo16_ds", 0, 14, 0 },
{ "fixup_ppc_tlsreg", 0, 0, 0 },
{ "fixup_ppc_nofixup", 0, 0, 0 }
};
Expand Down
14 changes: 0 additions & 14 deletions lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,6 @@ namespace {
virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const;
virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset);

virtual void sortRelocs(const MCAssembler &Asm,
std::vector<ELFRelocationEntry> &Relocs);
Expand Down Expand Up @@ -240,19 +239,6 @@ const MCSymbol *PPCELFObjectWriter::undefinedExplicitRelSym(const MCValue &Targe
return NULL;
}

void PPCELFObjectWriter::
adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
switch ((unsigned)Fixup.getKind()) {
case PPC::fixup_ppc_ha16:
case PPC::fixup_ppc_lo16:
case PPC::fixup_ppc_lo16_ds:
RelocOffset += 2;
break;
default:
break;
}
}

// The standard sorter only sorts on the r_offset field, but PowerPC can
// have multiple relocations at the same offset. Sort secondarily on the
// relocation type to avoid nondeterminism.
Expand Down
8 changes: 4 additions & 4 deletions lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -142,7 +142,7 @@ unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);

// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_ha16));
return 0;
}
Expand All @@ -153,7 +153,7 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);

// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
return 0;
}
Expand All @@ -170,7 +170,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;

// Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
return RegBits;
}
Expand All @@ -188,7 +188,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;

// Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16_ds));
return RegBits;
}
Expand Down
84 changes: 42 additions & 42 deletions test/MC/PowerPC/ppc64-fixups.s
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Original file line number Diff line number Diff line change
Expand Up @@ -8,113 +8,113 @@
# FIXME: .TOC.@tocbase

# CHECK: li 3, target@l # encoding: [0x38,0x60,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
li 3, target@l

# CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
addis 3, 3, target@ha

# CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
lis 3, target@ha

# CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
addi 4, 3, target@l

# CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
lwz 1, target@l(3)

# CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO_DS target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
ld 1, target@l(3)

# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target@toc, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
ld 1, target@toc(2)

# CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
addis 3, 2, target@toc@ha

# CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
addi 4, 3, target@toc@l

# CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
lwz 1, target@toc@l(3)

# CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
ld 1, target@toc@l(3)

# FIXME: @tls


# CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
addis 3, 2, target@tprel@ha

# CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
addi 3, 3, target@tprel@l

# CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
addis 3, 2, target@dtprel@ha

# CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
addi 3, 3, target@dtprel@l


# CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
addis 3, 2, target@got@tprel@ha

# CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
ld 1, target@got@tprel@l(3)


# CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
addis 3, 2, target@got@tlsgd@ha

# CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
addi 3, 3, target@got@tlsgd@l


# CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
addis 3, 2, target@got@tlsld@ha

# CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A]
# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO target 0x0
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_lo16
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
addi 3, 3, target@got@tlsld@l

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