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Added getTargetLowering() to TargetMachine. Refactored targets to sup…
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…port this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
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Evan Cheng committed Mar 13, 2006
1 parent e617b08 commit c4c6257
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Showing 27 changed files with 97 additions and 66 deletions.
8 changes: 4 additions & 4 deletions lib/Target/IA64/IA64.h
Original file line number Diff line number Diff line change
Expand Up @@ -18,26 +18,26 @@

namespace llvm {

class TargetMachine;
class IA64TargetMachine;
class FunctionPass;
class IntrinsicLowering;

/// createIA64DAGToDAGInstructionSelector - This pass converts an LLVM
/// function into IA64 machine code in a sane, DAG->DAG transform.
///
FunctionPass *createIA64DAGToDAGInstructionSelector(TargetMachine &TM);
FunctionPass *createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM);

/// createIA64BundlingPass - This pass adds stop bits and bundles
/// instructions.
///
FunctionPass *createIA64BundlingPass(TargetMachine &TM);
FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM);

/// createIA64CodePrinterPass - Returns a pass that prints the IA64
/// assembly code for a MachineFunction to the given output stream,
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form.
///
FunctionPass *createIA64CodePrinterPass(std::ostream &o,TargetMachine &tm);
FunctionPass *createIA64CodePrinterPass(std::ostream &o, IA64TargetMachine &tm);

} // End llvm namespace

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3 changes: 2 additions & 1 deletion lib/Target/IA64/IA64AsmPrinter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -374,7 +374,8 @@ bool IA64AsmPrinter::doFinalization(Module &M) {
/// assembly code for a MachineFunction to the given output stream, using
/// the given target machine description.
///
FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,TargetMachine &tm){
FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,
IA64TargetMachine &tm) {
return new IA64AsmPrinter(o, tm);
}

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6 changes: 3 additions & 3 deletions lib/Target/IA64/IA64Bundling.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,9 @@ namespace {
/// Target machine description which we query for reg. names, data
/// layout, etc.
///
TargetMachine &TM;
IA64TargetMachine &TM;

IA64BundlingPass(TargetMachine &tm) : TM(tm) { }
IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { }

virtual const char *getPassName() const {
return "IA64 (Itanium) Bundling Pass";
Expand All @@ -64,7 +64,7 @@ namespace {
/// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
/// and arranges the result into bundles.
///
FunctionPass *llvm::createIA64BundlingPass(TargetMachine &tm) {
FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
return new IA64BundlingPass(tm);
}

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7 changes: 4 additions & 3 deletions lib/Target/IA64/IA64ISelDAGToDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,8 @@ namespace {
IA64TargetLowering IA64Lowering;
unsigned GlobalBaseReg;
public:
IA64DAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
IA64DAGToDAGISel(IA64TargetMachine &TM)
: SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}

virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
Expand Down Expand Up @@ -621,7 +621,8 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
/// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
/// into an IA64-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
FunctionPass
*llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
return new IA64DAGToDAGISel(TM);
}

3 changes: 2 additions & 1 deletion lib/Target/IA64/IA64TargetMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,8 @@ unsigned IA64TargetMachine::getModuleMatchQuality(const Module &M) {
IA64TargetMachine::IA64TargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS)
: TargetMachine("IA64", IL, true),
FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0) { // FIXME? check this stuff
FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
TLInfo(*this) { // FIXME? check this stuff
}

// addPassesToEmitFile - We currently use all of the same passes as the JIT
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11 changes: 7 additions & 4 deletions lib/Target/IA64/IA64TargetMachine.h
Original file line number Diff line number Diff line change
Expand Up @@ -18,20 +18,23 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/PassManager.h"
#include "IA64InstrInfo.h"
#include "IA64ISelLowering.h"

namespace llvm {
class IntrinsicLowering;

class IA64TargetMachine : public TargetMachine {
IA64InstrInfo InstrInfo;
TargetFrameInfo FrameInfo;
IA64InstrInfo InstrInfo;
TargetFrameInfo FrameInfo;
//IA64JITInfo JITInfo;
IA64TargetLowering TLInfo;
public:
IA64TargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS);

virtual const IA64InstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const IA64InstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual IA64TargetLowering *getTargetLowering() { return &TLInfo; }
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
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8 changes: 4 additions & 4 deletions lib/Target/PowerPC/PPC.h
Original file line number Diff line number Diff line change
Expand Up @@ -20,16 +20,16 @@
namespace llvm {

class FunctionPass;
class TargetMachine;
class PPCTargetMachine;

enum PPCTargetEnum {
TargetDefault, TargetAIX, TargetDarwin
};

FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(TargetMachine &TM);
FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createDarwinAsmPrinter(std::ostream &OS, PPCTargetMachine &TM);
FunctionPass *createAIXAsmPrinter(std::ostream &OS, PPCTargetMachine &TM);

extern PPCTargetEnum PPCTarget;
} // end namespace llvm;
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5 changes: 3 additions & 2 deletions lib/Target/PowerPC/PPCAsmPrinter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -307,15 +307,16 @@ namespace {
/// code for a MachineFunction to the given output stream, in a format that the
/// Darwin assembler can deal with.
///
FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o,
PPCTargetMachine &tm) {
return new DarwinAsmPrinter(o, tm);
}

/// createAIXAsmPrinterPass - Returns a pass that prints the PPC assembly code
/// for a MachineFunction to the given output stream, in a format that the
/// AIX 5L assembler can deal with.
///
FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, PPCTargetMachine &tm) {
return new AIXAsmPrinter(o, tm);
}

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7 changes: 4 additions & 3 deletions lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,9 @@ namespace {
PPCTargetLowering PPCLowering;
unsigned GlobalBaseReg;
public:
PPCDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
PPCDAGToDAGISel(PPCTargetMachine &TM)
: SelectionDAGISel(PPCLowering),
PPCLowering(*TM.getTargetLowering()){}

virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
Expand Down Expand Up @@ -1140,7 +1141,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
/// createPPCISelDag - This pass converts a legalized DAG into a
/// PowerPC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
return new PPCDAGToDAGISel(TM);
}

8 changes: 8 additions & 0 deletions lib/Target/PowerPC/PPCISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@
#include "PPCISelLowering.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
Expand Down Expand Up @@ -1174,3 +1175,10 @@ isOperandValidForConstraint(SDOperand Op, char Letter) {
// Handle standard constraint letters.
return TargetLowering::isOperandValidForConstraint(Op, Letter);
}

/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode.
bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
// PPC allows a sign-extended 16-bit immediate field.
return (V > -(1 << 16) && V < (1 << 16)-1);
}
4 changes: 4 additions & 0 deletions lib/Target/PowerPC/PPCISelLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,10 @@ namespace llvm {
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);

/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode.
virtual bool isLegalAddressImmediate(int64_t V) const;
};
}

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6 changes: 3 additions & 3 deletions lib/Target/PowerPC/PPCJITInfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -17,13 +17,13 @@
#include "llvm/Target/TargetJITInfo.h"

namespace llvm {
class TargetMachine;
class PPCTargetMachine;

class PPCJITInfo : public TargetJITInfo {
protected:
TargetMachine &TM;
PPCTargetMachine &TM;
public:
PPCJITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;}
PPCJITInfo(PPCTargetMachine &tm) : TM(tm) {useGOT = 0;}

/// addPassesToJITCompile - Add passes to the specified pass manager to
/// implement a fast dynamic compiler for this target. Return true if this
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2 changes: 1 addition & 1 deletion lib/Target/PowerPC/PPCTargetMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
const std::string &FS)
: TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 2, 1, 1),
Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) {
if (TargetDefault == PPCTarget) {
if (Subtarget.isAIX()) PPCTarget = TargetAIX;
if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
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3 changes: 3 additions & 0 deletions lib/Target/PowerPC/PPCTargetMachine.h
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include "PPCSubtarget.h"
#include "PPCJITInfo.h"
#include "PPCInstrInfo.h"
#include "PPCISelLowering.h"
#include "llvm/Target/TargetMachine.h"

namespace llvm {
Expand All @@ -31,6 +32,7 @@ class PPCTargetMachine : public TargetMachine {
PPCSubtarget Subtarget;
PPCFrameInfo FrameInfo;
PPCJITInfo JITInfo;
PPCTargetLowering TLInfo;
InstrItineraryData InstrItins;
public:
PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
Expand All @@ -40,6 +42,7 @@ class PPCTargetMachine : public TargetMachine {
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual PPCTargetLowering *getTargetLowering() { return &TLInfo; }
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
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8 changes: 4 additions & 4 deletions lib/Target/X86/X86.h
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@

namespace llvm {

class TargetMachine;
class X86TargetMachine;
class PassManager;
class FunctionPass;
class IntrinsicLowering;
Expand All @@ -28,7 +28,7 @@ class MachineCodeEmitter;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
FunctionPass *createX86ISelDag(TargetMachine &TM);
FunctionPass *createX86ISelDag(X86TargetMachine &TM);

/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
Expand All @@ -40,7 +40,7 @@ FunctionPass *createX86FloatingPointStackifierPass();
/// assembly code for a MachineFunction to the given output stream,
/// using the given target machine description.
///
FunctionPass *createX86CodePrinterPass(std::ostream &o, TargetMachine &tm);
FunctionPass *createX86CodePrinterPass(std::ostream &o, X86TargetMachine &tm);

/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.
Expand All @@ -50,7 +50,7 @@ FunctionPass *createX86CodeEmitterPass(MachineCodeEmitter &MCE);
/// code as an ELF object file.
///
void addX86ELFObjectWriterPass(PassManager &FPM,
std::ostream &o, TargetMachine &tm);
std::ostream &o, X86TargetMachine &tm);

/// createX86EmitCodeToMemory - Returns a pass that converts a register
/// allocated function into raw machine code in a dynamically
Expand Down
1 change: 0 additions & 1 deletion lib/Target/X86/X86ATTAsmPrinter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@
#include "llvm/Target/TargetOptions.h"
#include <iostream>
using namespace llvm;
using namespace x86;

/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
Expand Down
4 changes: 1 addition & 3 deletions lib/Target/X86/X86ATTAsmPrinter.h
Original file line number Diff line number Diff line change
Expand Up @@ -18,10 +18,9 @@
#include "llvm/CodeGen/ValueTypes.h"

namespace llvm {
namespace x86 {

struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
X86ATTAsmPrinter(std::ostream &O, TargetMachine &TM)
X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM)
: X86SharedAsmPrinter(O, TM) { }

virtual const char *getPassName() const {
Expand Down Expand Up @@ -69,7 +68,6 @@ struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
bool runOnMachineFunction(MachineFunction &F);
};

} // end namespace x86
} // end namespace llvm

#endif
10 changes: 5 additions & 5 deletions lib/Target/X86/X86AsmPrinter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -14,21 +14,20 @@
//
//===----------------------------------------------------------------------===//

#include "X86AsmPrinter.h"
#include "X86ATTAsmPrinter.h"
#include "X86IntelAsmPrinter.h"
#include "X86Subtarget.h"
#include "X86.h"
#include "llvm/Constants.h"
#include "llvm/Module.h"
#include "llvm/Type.h"
#include "llvm/Assembly/Writer.h"
#include "llvm/Support/Mangler.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm;
using namespace x86;

Statistic<> llvm::x86::EmittedInsts("asm-printer",
"Number of machine instrs printed");
Statistic<> llvm::EmittedInsts("asm-printer",
"Number of machine instrs printed");

enum AsmWriterFlavorTy { att, intel };
cl::opt<AsmWriterFlavorTy>
Expand Down Expand Up @@ -210,7 +209,8 @@ bool X86SharedAsmPrinter::doFinalization(Module &M) {
/// for a MachineFunction to the given output stream, using the given target
/// machine description.
///
FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
X86TargetMachine &tm){
switch (AsmWriterFlavor) {
default:
assert(0 && "Unknown asm flavor!");
Expand Down
5 changes: 2 additions & 3 deletions lib/Target/X86/X86AsmPrinter.h
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
#define X86ASMPRINTER_H

#include "X86.h"
#include "X86TargetMachine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/CodeGen/MachineDebugInfo.h"
Expand All @@ -25,7 +26,6 @@


namespace llvm {
namespace x86 {

extern Statistic<> EmittedInsts;

Expand Down Expand Up @@ -56,7 +56,7 @@ X86DwarfWriter(std::ostream &o, AsmPrinter *ap)
struct X86SharedAsmPrinter : public AsmPrinter {
X86DwarfWriter DW;

X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM)
X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM)
: AsmPrinter(O, TM), DW(O, this), forDarwin(false) { }

bool doInitialization(Module &M);
Expand Down Expand Up @@ -90,7 +90,6 @@ struct X86SharedAsmPrinter : public AsmPrinter {
}
};

} // end namespace x86
} // end namespace llvm

#endif
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