Fix Svinval rs1 encodings (riscv#78)

liweiwei90 · Aug 3, 2021 · e6f08c1 · e6f08c1
1 parent a4069bc
commit e6f08c1
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/opcodes-svinval b/opcodes-svinval
@@ -1,6 +1,6 @@
 # Svinval
-sinval.vma      11..7=0 rs1 rs2        31..25=0x0b  14..12=0 6..2=0x1C 1..0=3
-sfence.w.inval  11..7=0 rs1 24..20=0x0 31..25=0x0c  14..12=0 6..2=0x1C 1..0=3
-sfence.inval.ir 11..7=0 rs1 24..20=0x1 31..25=0x0c  14..12=0 6..2=0x1C 1..0=3
-hinval.vvma     11..7=0 rs1 rs2        31..25=0x1b  14..12=0 6..2=0x1C 1..0=3
-hinval.gvma     11..7=0 rs1 rs2        31..25=0x3b  14..12=0 6..2=0x1C 1..0=3
+sinval.vma      11..7=0 rs1        rs2        31..25=0x0b  14..12=0 6..2=0x1C 1..0=3
+sfence.w.inval  11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c  14..12=0 6..2=0x1C 1..0=3
+sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c  14..12=0 6..2=0x1C 1..0=3
+hinval.vvma     11..7=0 rs1        rs2        31..25=0x1b  14..12=0 6..2=0x1C 1..0=3
+hinval.gvma     11..7=0 rs1        rs2        31..25=0x3b  14..12=0 6..2=0x1C 1..0=3