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Commits on Apr 30, 2018

• linux-user: set minimum uname for RISC-V

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Commits on Apr 16, 2018

• fpu/softfloat: check for Inf / x or 0 / x before /0

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• fpu/softfloat: raise float_invalid for NaN/Inf in round_to_int_and_pack

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Commits on Mar 13, 2018

• .travis.yml: add --disable-user with the rest of the disables

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• .travis.yml: split default config into system and user

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• .travis.yml: drop setting default log output

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Commits on Mar 12, 2018

• scripts/replay-dump.py: replay log dumper

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• replay: push replay_mutex_lock up the call tree

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• replay: make locking visible outside replay code

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• replay/replay-internal.c: track holding of replay_lock

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• replay/replay.c: bump REPLAY_VERSION again

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Commits on Mar 8, 2018

• .shippable.yml: disable powerpc-cross image

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Commits on Mar 1, 2018

• arm/translate-a64: add all single op FP16 to handle_fp_1src_half

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• arm/translate-a64: implement simd_scalar_three_reg_same_fp16

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• arm/translate-a64: add all FP16 ops in simd_scalar_pairwise

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• arm/translate-a64: add FP16 FMOV to simd_mod_imm

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• arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16

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• arm/helper.c: re-factor rsqrte and add rsqrte_f16

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• arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16

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• arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

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• arm/translate-a64: add FP16 FRECPE

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• arm/helper.c: re-factor recpe and add recepe_f16

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• arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

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• arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16

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• arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16

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• arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16

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• arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

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• arm/translate-a64: initial decode for simd_two_reg_misc_fp16

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• arm/translate-a64: add FP16 x2 ops for simd_indexed

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• arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed

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• arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16

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• arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16

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• arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16

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• arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16

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• arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16

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