Skip to content

Commit

Permalink
Update interconn.md
Browse files Browse the repository at this point in the history
  • Loading branch information
luoguojie authored Oct 13, 2021
1 parent 27d74e3 commit 1cd41de
Showing 1 changed file with 5 additions and 3 deletions.
8 changes: 5 additions & 3 deletions docs/sip/interconn.md
Original file line number Diff line number Diff line change
@@ -1,10 +1,12 @@
### Network-on-Chip (NoC)
- [PyOCN](https://github.com/cornell-brg/pymtl3-net) (Cornell), under [BSD 3-Clause License](https://github.com/cornell-brg/pymtl3-net/blob/master/LICENSE)
+ [PyOCN](https://github.com/cornell-brg/pymtl3-net) (Cornell), under [BSD 3-Clause License](https://github.com/cornell-brg/pymtl3-net/blob/master/LICENSE)
- PyOCN (PyMTL3-net) is a parameterizable and powerful OCN (on-chip network) generator to generate synthesizable Verilog for different OCNs based on user-specified configurations (e.g., network size, topology, number of virtual channels, routing strategy, switching arbitration, etc.).
- [OpenSoC Fabric](https://github.com/LBL-CoDEx/OpenSoCFabric) (Berkeley Lab)
+ [OpenSoC Fabric](https://github.com/LBL-CoDEx/OpenSoCFabric) (Berkeley Lab)
- An on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator
- [LISNoC](https://github.com/TUM-LIS/lisnoc) (TUM)
+ [LISNoC](https://github.com/TUM-LIS/lisnoc) (TUM)
- A free Network-on-Chip implementation, mainly for academic or teaching purposes
+ [OpenSMART](https://github.com/hyoukjun/OpenSMART) (GaTech), under [MIT License](https://github.com/hyoukjun/OpenSMART/blob/master/LICENSE)
- Single-Cycle Multi-hop NoC Generator in BSV and Chisel.

### NoC Simulators
- [Noxim](https://github.com/davidepatti/noxim) (Univ. of Catania), under [GNU General Public License v2.0](https://github.com/davidepatti/noxim/blob/master/doc/LICENSE.txt)
Expand Down

0 comments on commit 1cd41de

Please sign in to comment.