axi_xbar: Fix signal width for single master port

CHANGELOG.md

@@ -12,6 +12,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 ### Changed
 
 ### Fixed
+- `axi_xbar`: Fix signal width for single master port.  Before this fix, a crossbar instantiated
+  with a single master port would contain arrays with incorrect dimensions.
 
 
 ## 0.31.0 - 2021-12-07

src/axi_xbar.sv

@@ -15,7 +15,9 @@
 
 // axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.
 // See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports.
-module axi_xbar #(
+module axi_xbar
+import cf_math_pkg::idx_width;
+#(
   parameter axi_pkg::xbar_cfg_t Cfg = '0,
   parameter bit  ATOPs              = 1'b1,
   parameter type slv_aw_chan_t      = logic,
@@ -33,21 +35,21 @@ module axi_xbar #(
   parameter type mst_resp_t         = logic,
   parameter type rule_t             = axi_pkg::xbar_rule_64_t
 ) (
-  input  logic                                                       clk_i,
-  input  logic                                                       rst_ni,
-  input  logic                                                       test_i,
-  input  slv_req_t  [Cfg.NoSlvPorts-1:0]                             slv_ports_req_i,
-  output slv_resp_t [Cfg.NoSlvPorts-1:0]                             slv_ports_resp_o,
-  output mst_req_t  [Cfg.NoMstPorts-1:0]                             mst_ports_req_o,
-  input  mst_resp_t [Cfg.NoMstPorts-1:0]                             mst_ports_resp_i,
-  input  rule_t     [Cfg.NoAddrRules-1:0]                            addr_map_i,
-  input  logic      [Cfg.NoSlvPorts-1:0]                             en_default_mst_port_i,
-  input  logic      [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_mst_port_i
+  input  logic                                                          clk_i,
+  input  logic                                                          rst_ni,
+  input  logic                                                          test_i,
+  input  slv_req_t  [Cfg.NoSlvPorts-1:0]                                slv_ports_req_i,
+  output slv_resp_t [Cfg.NoSlvPorts-1:0]                                slv_ports_resp_o,
+  output mst_req_t  [Cfg.NoMstPorts-1:0]                                mst_ports_req_o,
+  input  mst_resp_t [Cfg.NoMstPorts-1:0]                                mst_ports_resp_i,
+  input  rule_t     [Cfg.NoAddrRules-1:0]                               addr_map_i,
+  input  logic      [Cfg.NoSlvPorts-1:0]                                en_default_mst_port_i,
+  input  logic      [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
 );
 
   typedef logic [Cfg.AxiAddrWidth-1:0]           addr_t;
   // to account for the decoding error slave
-  typedef logic [$clog2(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t;
+  typedef logic [idx_width(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t;
 
   // signals from the axi_demuxes, one index more for decode error
   slv_req_t  [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0]  slv_reqs;
@@ -61,10 +63,10 @@ module axi_xbar #(
   slv_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps;
 
   for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux
-    logic [$clog2(Cfg.NoMstPorts)-1:0] dec_aw,        dec_ar;
-    mst_port_idx_t                     slv_aw_select, slv_ar_select;
-    logic                              dec_aw_valid,  dec_aw_error;
-    logic                              dec_ar_valid,  dec_ar_error;
+    logic [idx_width(Cfg.NoMstPorts)-1:0] dec_aw,        dec_ar;
+    mst_port_idx_t                        slv_aw_select, slv_ar_select;
+    logic                                 dec_aw_valid,  dec_aw_error;
+    logic                                 dec_ar_valid,  dec_ar_error;
 
     addr_decode #(
       .NoIndices  ( Cfg.NoMstPorts  ),
@@ -239,19 +241,21 @@ endmodule
 `include "axi/assign.svh"
 `include "axi/typedef.svh"
 
-module axi_xbar_intf #(
+module axi_xbar_intf
+import cf_math_pkg::idx_width;
+#(
   parameter int unsigned AXI_USER_WIDTH =  0,
   parameter axi_pkg::xbar_cfg_t Cfg     = '0,
   parameter type rule_t                 = axi_pkg::xbar_rule_64_t
 ) (
-  input  logic                                                    clk_i,
-  input  logic                                                    rst_ni,
-  input  logic                                                    test_i,
-  AXI_BUS.Slave                                                   slv_ports [Cfg.NoSlvPorts-1:0],
-  AXI_BUS.Master                                                  mst_ports [Cfg.NoMstPorts-1:0],
-  input  rule_t [Cfg.NoAddrRules-1:0]                             addr_map_i,
-  input  logic  [Cfg.NoSlvPorts-1:0]                              en_default_mst_port_i,
-  input  logic  [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0]  default_mst_port_i
+  input  logic                                                      clk_i,
+  input  logic                                                      rst_ni,
+  input  logic                                                      test_i,
+  AXI_BUS.Slave                                                     slv_ports [Cfg.NoSlvPorts-1:0],
+  AXI_BUS.Master                                                    mst_ports [Cfg.NoMstPorts-1:0],
+  input  rule_t [Cfg.NoAddrRules-1:0]                               addr_map_i,
+  input  logic  [Cfg.NoSlvPorts-1:0]                                en_default_mst_port_i,
+  input  logic  [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
 );
 
   localparam int unsigned AxiIdWidthMstPorts = Cfg.AxiIdWidthSlvPorts + $clog2(Cfg.NoSlvPorts);