delay module reorg

lycchang · May 19, 2021 · 4971291 · 4971291
1 parent b262613
commit 4971291
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Showing 10 changed files with 9 additions and 1 deletion.
diff --git a/base/general/rtl/LutFixedDelay.vhd → base/delay/rtl/LutFixedDelay.vhd b/base/general/rtl/LutFixedDelay.vhd → base/delay/rtl/LutFixedDelay.vhd
diff --git a/base/general/rtl/SlvDelay.vhd → base/delay/rtl/SlvDelay.vhd b/base/general/rtl/SlvDelay.vhd → base/delay/rtl/SlvDelay.vhd
diff --git a/base/general/rtl/SlvDelayFifo.vhd → base/delay/rtl/SlvDelayFifo.vhd b/base/general/rtl/SlvDelayFifo.vhd → base/delay/rtl/SlvDelayFifo.vhd
diff --git a/base/general/rtl/SlvDelayRam.vhd → base/delay/rtl/SlvDelayRam.vhd b/base/general/rtl/SlvDelayRam.vhd → base/delay/rtl/SlvDelayRam.vhd
diff --git a/base/general/rtl/SlvFixedDelay.vhd → base/delay/rtl/SlvFixedDelay.vhd b/base/general/rtl/SlvFixedDelay.vhd → base/delay/rtl/SlvFixedDelay.vhd
diff --git a/base/delay/ruckus.tcl b/base/delay/ruckus.tcl
@@ -0,0 +1,8 @@
+# Load RUCKUS library
+source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
+
+# Load Source Code
+loadSource -lib surf -dir "$::DIR_PATH/rtl"
+
+# Load Simulation
+loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
diff --git a/base/general/tb/SlvDelayRamTb.vhd → base/delay/tb/SlvDelayRamTb.vhd b/base/general/tb/SlvDelayRamTb.vhd → base/delay/tb/SlvDelayRamTb.vhd
diff --git a/base/general/ruckus.tcl b/base/general/ruckus.tcl
@@ -4,7 +4,6 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 # Load Source Code
 loadSource -lib surf -dir "$::DIR_PATH/rtl"
 loadSource -lib surf -dir "$::DIR_PATH/ip_integrator"
-loadSource -lib surf -dir "$::DIR_PATH/xilinx"
 
 # Load Simulation
 loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
diff --git a/base/ruckus.tcl b/base/ruckus.tcl
@@ -2,6 +2,7 @@
 source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 
 # Load ruckus files
+loadRuckusTcl "$::DIR_PATH/delay"
 loadRuckusTcl "$::DIR_PATH/fifo"
 loadRuckusTcl "$::DIR_PATH/general"
 loadRuckusTcl "$::DIR_PATH/ram"

diff --git a/base/general/xilinx/Srl16Delay.vhd → xilinx/general/rtl/Srl16Delay.vhd b/base/general/xilinx/Srl16Delay.vhd → xilinx/general/rtl/Srl16Delay.vhd