The Virtual Components Modeling Library contains a set of SystemC/TLM modeling primitives and component models that can be used to swiftly assemble system level simulators for embedded systems, i.e. Virtual Platforms. Its main design goal is to accelerate VP construction by providing a set of commonly used features, such as TLM sockets, Interrupt ports, I/O peripherals and registers. Based on these design primitives, TLM models for frequently deployed components are also provided, such as memories, memory-mapped buses, UARTs, etc.
A build guide for VCML can be found here.
Some basic documentation about this library and its models are provided in the doc directory.
| Project | About |
|---|---|
| vcml-cci | SystemC CCI integration for VCML |
| vcml-silkit | Vector SIL Kit integration for VCML |
A curated collection of existing contributions in the form of individual models or complete Virtual Platforms can be found on our community projects website at:
https://www.machineware.de/vcml-community
Please note that we currently cannot accept Pull Requests on GitHub. Contributions to VCML can be submitted as patch files via email instead.
This project is licensed under the Apache-2.0 license - see the LICENSE file for details.