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Commits on Dec 19, 2016

• [X86] When recognizing vector loads or VZEXT_LOAD in selectScalarSSELoad make sure we pass the load's user rather than load itself to the second operand of IsLegalToFold.

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• [TableGen] Use 'unsigned' instead of 'bool' in a place where the code conditionally assigns numeric values. They happen to be 0 and 1 so this is NFC.

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• [X86] Remove all of the patterns that use X86ISD:FAND/FXOR/FOR/FANDN except for the ones needed for SSE1. Anything SSE2 or above uses the integer ISD opcode.

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Commits on Dec 18, 2016

• [X86][SSE][AVX-512] Convert FAND/FOR/FXOR/FANDN nodes to integer operations if they are available. This will allow a bunch of patterns to be removed.

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• [AVX-512] Use EVEX encoded XOR instruction for zeroing scalar registers when DQI and VLX instructions are available.

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• [AVX-512] Make sure VLX is also enabled before using EVEX encoded logic ops for scalars. I missed this in r290049.

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Commits on Dec 17, 2016

• [AVX-512] Use EVEX encoded logic operations for scalar types when they are available. This gives the register allocator more registers to work with.

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• [AVX-512] Update scalar logic test to show missed opportunity to use EVEX encoded logic instructions to get more registers to use.

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• [InstCombine] Simplify code slightly. NFC

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Commits on Dec 15, 2016

• [AVX-512][InstCombine] Add masked scalar FMA intrinsics to SimplifyDemandedVectorElts.

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Commits on Dec 14, 2016

• [X86][InstCombine] Handle demanded elements for operand of AVX-512 scalar floating point to integer conversion intrinsics.

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• [X86][InstCombine] Teach SimplifyDemandedVectorElts to handle masked scalar add/sub/mul/div/max/min intrinsics better.

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• [X86][InstCombine] Handle scalar fmadd intrinsics correctly in SimplifyDemandedVectorElts.

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• [X86][InstCombine] Teach SimplifyDemandedVectorElts to handle scalar round intrinsics more correctly.

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• [X86][InstCombine] Teach SimplifyDemandedVectorElts to handle scalar min/max/cmp intrinsics more correctly.

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Commits on Dec 13, 2016

• [X86][InstCombine] Fix SimplifyDemandedVectorElts to handle frcz scalar intrinsics correctly.

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Commits on Dec 12, 2016

• [X86] Teach selectScalarSSELoad to accept full 128-bit vector loads and the X86ISD::VZEXT_LOAD opcode.

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• [X86] Change CMPSS/CMPSD intrinsic instructions to use sse_load_f32/f64 as its memory pattern instead of full vector load.

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• [X86] Remove some intrinsic instructions from hasPartialRegUpdate

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Commits on Dec 11, 2016

• [InstCombine][XOP] The instructions for the scalar frcz intrinsics are defined to put 0 in the upper bits, not pass bits through like other intrinsics. So we should return a zero vector instead.

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• [X86][InstCombine] Add support for scalar FMA intrinsics to SimplifyDemandedVectorElts.

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• [X86][InstCombine] Add the test cases for r289370, r289371, and r289372.

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• [X86][InstCombine] Teach InstCombineCalls to simplify demanded elements for scalar FMA intrinsics.

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• [AVX-512][InstCombine] Teach InstCombineCalls how to simplify demanded for scalar cmp intrinsics with masking and rounding.

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• [AVX-512][InstCombine] Teach InstCombineCalls how to simplify demanded elements for scalar add,div,mul,sub,max,min intrinsics with masking and rounding.

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• [AVX-512][InstCombine] Add 512-bit vpermilvar intrinsics to InstCombineCalls to match 128 and 256-bit.

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• [X86] Fix a comment to say 'an FMA' instead of 'a FMA'. NFC

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• [X86] Remove masking from 512-bit VPERMIL intrinsics in preparation for being able to constant fold them in InstCombineCalls like we do for 128/256-bit.

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• [X86][InstCombine] Teach InstCombineCalls to turn pshufb intrinsic into a shufflevector if the indices are constant.

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Commits on Dec 10, 2016

• [X86] Remove masking from 512-bit PSHUFB intrinsics in preparation for being able to constant fold it in InstCombineCalls like we do for 128/256-bit.

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• [AVX-512] Remove 128/256 masked vpermil instrinsics and autoupgrade to a select around the unmasked avx1 intrinsics.

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• [X86][IR] Move the autoupgrading of store intrinsics out of the main nested if/else chain. This should buy a little more time against the MSVC limit mentioned in PR31034.

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• [AVX-512] Add support for lowering (v2i64 (fp_to_sint (v2f32))) to vcvttps2uqq when AVX512DQ and AVX512VL are available.

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• [X86] Clarify indentation. NFC

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• [X86] Combine LowerFP_TO_SINT and LowerFP_TO_UINT. They only differ by a single boolean flag passed to a helper function. Just check the opcode and create the flag.

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