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Merge tag 'iommu-updates-v3.5' of git://git.kernel.org/pub/scm/linux/…
…kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: "Not much stuff this time. The only change to the IOMMU core code is the addition of a handle to the fault handling code. A few updates to the AMD IOMMU driver to work around new errata. The other patches are mostly fixes and enhancements to the existing ARM IOMMU drivers and documentation updates. A new IOMMU driver for the Exynos platform was also underway but got merged via the Samsung tree and is not part of this tree." * tag 'iommu-updates-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: Documentation: kernel-parameters.txt Add amd_iommu_dump iommu/core: pass a user-provided token to fault handlers iommu/tegra: gart: Fix register offset correctly iommu: OMAP: device detach on domain destroy iommu: tegra/gart: Add device tree support iommu: tegra/gart: use correct gart_device iommu/tegra: smmu: Print device name correctly iommu/amd: Add workaround for event log erratum iommu/amd: Check for the right TLP prefix bit dma-debug: release free_entries_lock before saving stack trace
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Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
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@@ -0,0 +1,14 @@ | ||
NVIDIA Tegra 20 GART | ||
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Required properties: | ||
- compatible: "nvidia,tegra20-gart" | ||
- reg: Two pairs of cells specifying the physical address and size of | ||
the memory controller registers and the GART aperture respectively. | ||
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Example: | ||
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gart { | ||
compatible = "nvidia,tegra20-gart"; | ||
reg = <0x7000f024 0x00000018 /* controller registers */ | ||
0x58000000 0x02000000>; /* GART aperture */ | ||
}; |
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Original file line number | Diff line number | Diff line change |
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@@ -29,15 +29,17 @@ | |
#include <linux/device.h> | ||
#include <linux/io.h> | ||
#include <linux/iommu.h> | ||
#include <linux/of.h> | ||
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#include <asm/cacheflush.h> | ||
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/* bitmap of the page sizes currently supported */ | ||
#define GART_IOMMU_PGSIZES (SZ_4K) | ||
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#define GART_CONFIG 0x24 | ||
#define GART_ENTRY_ADDR 0x28 | ||
#define GART_ENTRY_DATA 0x2c | ||
#define GART_REG_BASE 0x24 | ||
#define GART_CONFIG (0x24 - GART_REG_BASE) | ||
#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE) | ||
#define GART_ENTRY_DATA (0x2c - GART_REG_BASE) | ||
#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31) | ||
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#define GART_PAGE_SHIFT 12 | ||
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@@ -158,7 +160,7 @@ static int gart_iommu_attach_dev(struct iommu_domain *domain, | |
struct gart_client *client, *c; | ||
int err = 0; | ||
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gart = dev_get_drvdata(dev->parent); | ||
gart = gart_handle; | ||
if (!gart) | ||
return -EINVAL; | ||
domain->priv = gart; | ||
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@@ -422,13 +424,22 @@ const struct dev_pm_ops tegra_gart_pm_ops = { | |
.resume = tegra_gart_resume, | ||
}; | ||
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#ifdef CONFIG_OF | ||
static struct of_device_id tegra_gart_of_match[] __devinitdata = { | ||
{ .compatible = "nvidia,tegra20-gart", }, | ||
{ }, | ||
}; | ||
MODULE_DEVICE_TABLE(of, tegra_gart_of_match); | ||
#endif | ||
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static struct platform_driver tegra_gart_driver = { | ||
.probe = tegra_gart_probe, | ||
.remove = tegra_gart_remove, | ||
.driver = { | ||
.owner = THIS_MODULE, | ||
.name = "tegra-gart", | ||
.pm = &tegra_gart_pm_ops, | ||
.of_match_table = of_match_ptr(tegra_gart_of_match), | ||
}, | ||
}; | ||
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@@ -448,4 +459,5 @@ module_exit(tegra_gart_exit); | |
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MODULE_DESCRIPTION("IOMMU API for GART in Tegra20"); | ||
MODULE_AUTHOR("Hiroshi DOYU <[email protected]>"); | ||
MODULE_ALIAS("platform:tegra-gart"); | ||
MODULE_LICENSE("GPL v2"); |
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