Skip to content

Commit

Permalink
drm/msm: update generated headers
Browse files Browse the repository at this point in the history 
Signed-off-by: Rob Clark <[email protected]>
  • Loading branch information
@robclark
robclark committed Jun 11, 2015
1 parent a5436e1 commit af6cb4c
Show file tree
Hide file tree
Showing 17 changed files with 1,359 additions and 143 deletions.
6 changes: 3 additions & 3 deletions drivers/gpu/drm/msm/adreno/a2xx.xml.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
Copyright (C) 2013-2014 by the following authors:
- Rob Clark <[email protected]> (robclark)
Expand Down
168 changes: 156 additions & 12 deletions drivers/gpu/drm/msm/adreno/a3xx.xml.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19)
Copyright (C) 2013-2014 by the following authors:
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <[email protected]> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
Expand Down Expand Up @@ -130,6 +130,10 @@ enum a3xx_tex_fmt {
TFMT_I420_Y = 24,
TFMT_I420_U = 26,
TFMT_I420_V = 27,
TFMT_ATC_RGB = 32,
TFMT_ATC_RGBA_EXPLICIT = 33,
TFMT_ETC1 = 34,
TFMT_ATC_RGBA_INTERPOLATED = 35,
TFMT_DXT1 = 36,
TFMT_DXT3 = 37,
TFMT_DXT5 = 38,
Expand Down Expand Up @@ -178,10 +182,13 @@ enum a3xx_tex_fmt {
TFMT_32_SINT = 92,
TFMT_32_32_SINT = 93,
TFMT_32_32_32_32_SINT = 95,
TFMT_RGTC2_SNORM = 112,
TFMT_RGTC2_UNORM = 113,
TFMT_RGTC1_SNORM = 114,
TFMT_RGTC1_UNORM = 115,
TFMT_ETC2_RG11_SNORM = 112,
TFMT_ETC2_RG11_UNORM = 113,
TFMT_ETC2_R11_SNORM = 114,
TFMT_ETC2_R11_UNORM = 115,
TFMT_ETC2_RGBA8 = 116,
TFMT_ETC2_RGB8A1 = 117,
TFMT_ETC2_RGB8 = 118,
};

enum a3xx_tex_fetchsize {
Expand Down Expand Up @@ -209,14 +216,24 @@ enum a3xx_color_fmt {
RB_R10G10B10A2_UNORM = 16,
RB_A8_UNORM = 20,
RB_R8_UNORM = 21,
RB_R16_FLOAT = 24,
RB_R16G16_FLOAT = 25,
RB_R16G16B16A16_FLOAT = 27,
RB_R11G11B10_FLOAT = 28,
RB_R16_SNORM = 32,
RB_R16G16_SNORM = 33,
RB_R16G16B16A16_SNORM = 35,
RB_R16_UNORM = 36,
RB_R16G16_UNORM = 37,
RB_R16G16B16A16_UNORM = 39,
RB_R16_SINT = 40,
RB_R16G16_SINT = 41,
RB_R16G16B16A16_SINT = 43,
RB_R16_UINT = 44,
RB_R16G16_UINT = 45,
RB_R16G16B16A16_UINT = 47,
RB_R32_FLOAT = 48,
RB_R32G32_FLOAT = 49,
RB_R32G32B32A32_FLOAT = 51,
RB_R32_SINT = 52,
RB_R32G32_SINT = 53,
Expand Down Expand Up @@ -265,6 +282,12 @@ enum a3xx_intp_mode {
FLAT = 1,
};

enum a3xx_repl_mode {
S = 1,
T = 2,
ONE_T = 3,
};

enum a3xx_tex_filter {
A3XX_TEX_NEAREST = 0,
A3XX_TEX_LINEAR = 1,
Expand Down Expand Up @@ -751,7 +774,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
{
return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
}

#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
Expand Down Expand Up @@ -854,6 +877,12 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode va
{
return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
}
#define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000
#define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12
static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
{
return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
}
#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000

Expand Down Expand Up @@ -1246,9 +1275,21 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v

#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105

#define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106
#define REG_A3XX_RB_STENCIL_INFO 0x00002106
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11
static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
{
return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
}

#define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107
#define REG_A3XX_RB_STENCIL_PITCH 0x00002107
#define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff
#define A3XX_RB_STENCIL_PITCH__SHIFT 0
static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
{
return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
}

#define REG_A3XX_RB_STENCILREFMASK 0x00002108
#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
Expand Down Expand Up @@ -1356,6 +1397,7 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
{
return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
}
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
Expand Down Expand Up @@ -1805,6 +1847,102 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }

static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c
#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030
#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0
#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300
#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00
#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
{
return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
}

#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a

Expand Down Expand Up @@ -2107,6 +2245,12 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9

#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003
#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
{
return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
}
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
Expand Down Expand Up @@ -2661,7 +2805,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
}

#define REG_A3XX_TEX_CONST_3 0x00000003
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0000000f
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x00007fff
#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
{
Expand Down
Loading

0 comments on commit af6cb4c

Please sign in to comment.