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DynaRec: add more instructions from the vita port, optimize a few things
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@cmf028 @masterfeizz
cmf028 authored and masterfeizz committed Dec 5, 2020
1 parent 719c783 commit ebe83e1
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Showing 4 changed files with 290 additions and 73 deletions.
66 changes: 62 additions & 4 deletions Source/SysCTR/DynaRec/arm/AssemblyWriterARM.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -300,7 +300,7 @@ void CAssemblyWriterARM::BIC_IMM(EArmReg rd, EArmReg rn, u32 imm, EArmReg temp)
}
else if (encOp2Imm(~imm, &enc))
{
AND_IMM(rd, rn, imm, temp);
AND_IMM(rd, rn, ~imm, temp);
}
else
{
Expand Down Expand Up @@ -583,19 +583,34 @@ void CAssemblyWriterARM::VSQRT(EArmVfpReg Sd, EArmVfpReg Sm)
EmitDWORD(0xeeb10ac0 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | ((Sm & 1) << 5) | ((Sm >> 1) & 15));
}

void CAssemblyWriterARM::VCMP(EArmVfpReg Sd, EArmVfpReg Sm)
void CAssemblyWriterARM::VABS(EArmVfpReg Sd, EArmVfpReg Sm)
{
EmitDWORD(0xeeb40a40 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | ((Sm & 1) << 5) | ((Sm >> 1) & 15));
EmitDWORD(0xeeb00ac0 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | ((Sm & 1) << 5) | ((Sm >> 1) & 15));
}

void CAssemblyWriterARM::VNEG(EArmVfpReg Sd, EArmVfpReg Sm)
{
EmitDWORD(0xeeb10a40 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | ((Sm & 1) << 5) | ((Sm >> 1) & 15));
}

void CAssemblyWriterARM::VCMP(EArmVfpReg Sd, EArmVfpReg Sm, u8 E)
{
EmitDWORD(0xeeb40a40 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | ((Sm & 1) << 5) | ((Sm >> 1) & 15) | (E << 7));

//vmrs APSR_nzcv, FPSCR @ Get the flags into APSR.
EmitDWORD(0xeef1fa10);
}

// round to zero
void CAssemblyWriterARM::VCVT_S32_F32(EArmVfpReg Sd, EArmVfpReg Sm)
{
EmitDWORD(0xeebd0ac0 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | ((Sm & 1)<<5) | ((Sm >> 1) & 15));
}

void CAssemblyWriterARM::VCVT_F64_F32(EArmVfpReg Dd, EArmVfpReg Sm)
{
EmitDWORD(0xeeb70ac0 | (((Dd >> 4) & 1) << 22) | ((Dd & 15) << 12) | ((Sm & 1) << 5) | ((Sm >> 1) & 15));
}

void CAssemblyWriterARM::VADD_D(EArmVfpReg Dd, EArmVfpReg Dn, EArmVfpReg Dm)
{
EmitDWORD(0xee300b00 | (((Dd >> 4) & 1) << 22) | ((Dn & 15) << 16) | ((Dd & 15) << 12) | (((Dn >> 4) & 1) << 7) | (((Dm >> 4) & 1) << 5) | (Dm & 15));
Expand Down Expand Up @@ -626,6 +641,11 @@ void CAssemblyWriterARM::VMOV_S( EArmVfpReg Dm, EArmReg Rt)
EmitDWORD(0xee000a10 | ((Dm >> 1) << 16) | (Rt << 12) | ((Dm & 0x1) << 7));
}

void CAssemblyWriterARM::VMOV_S( EArmVfpReg Dm, EArmVfpReg Rt)
{
EmitDWORD(0xeeb00a40 | ((Dm & 1) << 22) | (((Dm>>1) & 15) << 12) | ((Rt & 1) << 5) | ((Rt >> 1) & 15));
}

void CAssemblyWriterARM::VMOV_L(EArmReg Rt, EArmVfpReg Dm)
{
EmitDWORD(0xee100b10 | ((Dm) << 16) | (Rt << 12));
Expand All @@ -646,6 +666,21 @@ void CAssemblyWriterARM::VMOV_H(EArmVfpReg Dm, EArmReg Rt)
EmitDWORD(0xee200b10 | ((Dm) << 16) | (Rt << 12));
}

void CAssemblyWriterARM::VSQRT_D(EArmVfpReg Dd, EArmVfpReg Dm)
{
EmitDWORD(0xeeb10bc0 | (((Dd >> 4) & 1) << 22) | ((Dd & 15) << 12) | (((Dm >> 4) & 1) << 5) | (Dm & 15));
}

void CAssemblyWriterARM::VABS_D(EArmVfpReg Dd, EArmVfpReg Dm)
{
EmitDWORD(0xeeb00bc0 | (((Dd >> 4) & 1) << 22) | ((Dd & 15) << 12) | (((Dm >> 4) & 1) << 5) | (Dm & 15));
}

void CAssemblyWriterARM::VNEG_D(EArmVfpReg Dd, EArmVfpReg Dm)
{
EmitDWORD(0xeeb10b40 | (((Dd >> 4) & 1) << 22) | ((Dd & 15) << 12) | (((Dm >> 4) & 1) << 5) | (Dm & 15));
}

void CAssemblyWriterARM::VMOV(EArmVfpReg Dm, EArmReg Rt, EArmReg Rt2)
{
EmitDWORD(0xec400b10 | (Rt2 << 16) | (Rt << 12) | (Dm & 0b1111) | (((Dm >> 4) & 1) << 5));
Expand All @@ -656,6 +691,11 @@ void CAssemblyWriterARM::VMOV(EArmReg Rt, EArmReg Rt2, EArmVfpReg Dm)
EmitDWORD(0xec500b10 | (Rt2 << 16) | (Rt << 12) | (Dm & 0b1111) | (((Dm >> 4) & 1) << 5));
}

void CAssemblyWriterARM::VMOV( EArmVfpReg Dm, EArmVfpReg Rt)
{
EmitDWORD(0xeeb00b40 | (((Dm >> 4) & 1) << 22) | ((Dm & 15) << 12) | (((Rt >> 4) & 1) << 5) | (Rt & 15));
}

void CAssemblyWriterARM::VLDR_D(EArmVfpReg Dd, EArmReg Rn, s16 offset12)
{
EmitDWORD(0xed100b00 | ((offset12 < 0) ? 0 : 1) << 23 | (((Dd >> 4) & 1) << 22) | (Rn << 16) | ((Dd & 15) << 12) | ((abs(offset12) >> 2) & 255));
Expand All @@ -666,6 +706,24 @@ void CAssemblyWriterARM::VSTR_D(EArmVfpReg Dd, EArmReg Rn, s16 offset12)
EmitDWORD(0xed000b00 | ((offset12 < 0) ? 0 : 1) << 23 | (((Dd >> 4) & 1) << 22) | (Rn << 16) | ((Dd & 15) << 12) | ((abs(offset12) >> 2) & 255));
}

void CAssemblyWriterARM::VCMP_D(EArmVfpReg Dd, EArmVfpReg Dm, u8 E)
{
EmitDWORD(0xeeb40b40 | (((Dd >> 4) & 1) << 22) | ((Dd & 15) << 12) | (((Dm >> 4) & 1) << 5) | (Dm & 15) | (E << 7));

//vmrs APSR_nzcv, FPSCR @ Get the flags into APSR.
EmitDWORD(0xeef1fa10);
}

void CAssemblyWriterARM::VCVT_S32_F64(EArmVfpReg Sd, EArmVfpReg Dm)
{
EmitDWORD(0xeebd0bc0 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | (((Dm >> 4) & 1) << 5) | (Dm & 15));
}

void CAssemblyWriterARM::VCVT_F32_F64(EArmVfpReg Sd, EArmVfpReg Dm)
{
EmitDWORD(0xeeb70bc0 | ((Sd & 1) << 22) | (((Sd >> 1) & 15) << 12) | (((Dm >> 4) & 1) << 5) | (Dm & 15));
}

#ifdef DYNAREC_ARMV7
void CAssemblyWriterARM::MOVW(EArmReg reg, u16 imm)
{
Expand Down
17 changes: 14 additions & 3 deletions Source/SysCTR/DynaRec/arm/AssemblyWriterARM.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,23 +133,34 @@ class CAssemblyWriterARM
void VMUL (EArmVfpReg Sd, EArmVfpReg Sn, EArmVfpReg Sm);
void VDIV (EArmVfpReg Sd, EArmVfpReg Sn, EArmVfpReg Sm);
void VSQRT(EArmVfpReg Sd, EArmVfpReg Sm);
void VCMP (EArmVfpReg Sd, EArmVfpReg Sm);
void VABS (EArmVfpReg Sd, EArmVfpReg Sm);
void VNEG (EArmVfpReg Sd, EArmVfpReg Sm);
void VCMP (EArmVfpReg Sd, EArmVfpReg Sm, u8 E = 0);
void VCVT_S32_F32(EArmVfpReg Sd, EArmVfpReg Sm);

void VCVT_F64_F32(EArmVfpReg Dd, EArmVfpReg Sm);

void VMOV_S(EArmReg Rt, EArmVfpReg Dm);
void VMOV_S(EArmVfpReg Dm, EArmReg Rt);
void VMOV_S(EArmVfpReg Dm, EArmVfpReg Rt);
void VMOV_L(EArmReg Rt, EArmVfpReg Dm);
void VMOV_L(EArmVfpReg Dm, EArmReg Rt);
void VMOV_H(EArmReg Rt, EArmVfpReg Dm);
void VMOV_H(EArmVfpReg Dm, EArmReg Rt);
void VMOV (EArmVfpReg dm, EArmReg rt, EArmReg rt2);
void VMOV (EArmReg rt, EArmReg rt2, EArmVfpReg dm);
void VMOV (EArmVfpReg Dm, EArmVfpReg Rt);

void VADD_D (EArmVfpReg Dd, EArmVfpReg Dn, EArmVfpReg Dm);
void VSUB_D (EArmVfpReg Dd, EArmVfpReg Dn, EArmVfpReg Dm);
void VMUL_D (EArmVfpReg Dd, EArmVfpReg Dn, EArmVfpReg Dm);
void VDIV_D (EArmVfpReg Dd, EArmVfpReg Dn, EArmVfpReg Dm);

void VSQRT_D(EArmVfpReg Dd, EArmVfpReg Dm);
void VABS_D (EArmVfpReg Dd, EArmVfpReg Dm);
void VNEG_D (EArmVfpReg Dd, EArmVfpReg Dm);
void VCMP_D (EArmVfpReg Sd, EArmVfpReg Sm, u8 E = 0);
void VCVT_S32_F64(EArmVfpReg Sd, EArmVfpReg Dm);
void VCVT_F32_F64(EArmVfpReg Sd, EArmVfpReg Dm);

void VLDR_D (EArmVfpReg dd, EArmReg rn, s16 offset12);
void VSTR_D (EArmVfpReg dd, EArmReg rn, s16 offset12);

Expand Down
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