ARC: boards: add nsim-based board with hostlink uart support

Add nsim_hs3x_hostlink nsim-based board to test virtual UART emulated with hostlink channel. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Evgeniy Paltsev <[email protected]>
maxpark · Mar 17, 2023 · d4a5f18 · d4a5f18
1 parent 5657268
commit d4a5f18
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Showing 16 changed files with 198 additions and 15 deletions.
diff --git a/boards/arc/nsim/nsim-smp.dtsi b/boards/arc/nsim/nsim-smp.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "nsim.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	ici: intercore-interrupt-unit {

diff --git a/boards/arc/nsim/nsim-uart-hostlink.dtsi b/boards/arc/nsim/nsim-uart-hostlink.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2023, Synopsys Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	hostlink: hostlink {
+		compatible = "snps,hostlink-uart";
+		status = "okay";
+	};
+
+	chosen {
+		zephyr,console = &hostlink;
+		zephyr,shell-uart = &hostlink;
+	};
+};
diff --git a/boards/arc/nsim/nsim-uart-ns16550.dtsi b/boards/arc/nsim/nsim-uart-ns16550.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023, Synopsys Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	uart0: uart@f0000000 {
+		compatible = "ns16550";
+		clock-frequency = <50000000>;
+		reg = <0xf0000000 0x400>;
+		current-speed = <115200>;
+		interrupt-parent = <&intc>;
+		interrupts = <24 1>;
+		reg-shift = <2>;
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
diff --git a/boards/arc/nsim/nsim.dtsi b/boards/arc/nsim/nsim.dtsi
@@ -32,19 +32,4 @@
 		interrupts = <17 1>;
 		interrupt-parent = <&intc>;
 	};
-
-	uart0: uart@f0000000 {
-		compatible = "ns16550";
-		clock-frequency = <50000000>;
-		reg = <0xf0000000 0x400>;
-		current-speed = <115200>;
-		interrupt-parent = <&intc>;
-		interrupts = <24 1>;
-		reg-shift = <2>;
-	};
-
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-	};
 };
diff --git a/boards/arc/nsim/nsim_em.dtsi b/boards/arc/nsim/nsim_em.dtsi
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-ccm-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	cpus {

diff --git a/boards/arc/nsim/nsim_hs.dts b/boards/arc/nsim/nsim_hs.dts
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-ccm-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	model = "snps,nsim_hs";

diff --git a/boards/arc/nsim/nsim_hs3x_hostlink.dts b/boards/arc/nsim/nsim_hs3x_hostlink.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023, Synopsys Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "nsim.dtsi"
+#include "nsim-ccm-mem.dtsi"
+#include "nsim-uart-hostlink.dtsi"
+
+/ {
+	model = "snps,nsim_hs";
+	compatible = "snps,nsim_hs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <0>;
+		};
+	};
+};
diff --git a/boards/arc/nsim/nsim_hs3x_hostlink.yaml b/boards/arc/nsim/nsim_hs3x_hostlink.yaml
@@ -0,0 +1,14 @@
+identifier: nsim_hs3x_hostlink
+name: HS3x nSIM simulator
+type: sim
+simulation: nsim
+simulation_exec: nsimdrv
+arch: arc
+toolchain:
+  - zephyr
+  - cross-compile
+  - arcmwdt
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/boards/arc/nsim/nsim_hs3x_hostlink_defconfig b/boards/arc/nsim/nsim_hs3x_hostlink_defconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_NSIM=y
+CONFIG_SOC_NSIM_HS=y
+CONFIG_BOARD_NSIM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_ARC_EXCEPTION_DEBUG=y
+CONFIG_ARC_MPU_ENABLE=y
diff --git a/boards/arc/nsim/nsim_hs5x.dts b/boards/arc/nsim/nsim_hs5x.dts
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-flat-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	model = "snps,nsim_hs";

diff --git a/boards/arc/nsim/nsim_hs6x.dts b/boards/arc/nsim/nsim_hs6x.dts
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-flat-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	model = "snps,nsim_hs";

diff --git a/boards/arc/nsim/nsim_hs_flash_xip.dts b/boards/arc/nsim/nsim_hs_flash_xip.dts
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-flash-sram-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	model = "snps,nsim_hs";

diff --git a/boards/arc/nsim/nsim_hs_mpuv6.dts b/boards/arc/nsim/nsim_hs_mpuv6.dts
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-ccm-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	model = "snps,nsim_hs";

diff --git a/boards/arc/nsim/nsim_hs_sram.dts b/boards/arc/nsim/nsim_hs_sram.dts
@@ -8,6 +8,7 @@
 
 #include "nsim.dtsi"
 #include "nsim-flat-mem.dtsi"
+#include "nsim-uart-ns16550.dtsi"
 
 / {
 	model = "snps,nsim_hs";

diff --git a/boards/arc/nsim/support/mdb_hs3x_hostlink.args b/boards/arc/nsim/support/mdb_hs3x_hostlink.args
@@ -0,0 +1,44 @@
+	-arcv2hs
+	-core2
+	-arcnum=3
+	-rgf_num_banks=2
+	-rgf_banked_regs=32
+	-rgf_num_wr_ports=2
+	-Xatomic
+	-Xll64
+	-Xunaligned
+	-Xcode_density
+	-Xdiv_rem=radix4
+	-Xswap
+	-Xbitscan
+	-Xmpy_option=qmpyh
+	-Xshift_assist
+	-Xbarrel_shifter
+	-Xfpud_div
+	-Xfpu_mac
+	-Xtimer0
+	-Xtimer0_level=1
+	-Xtimer1
+	-Xtimer1_level=0
+	-Xrtc
+	-action_points=8
+	-Xstack_check
+	-interrupts=72
+	-interrupt_priorities=2
+	-ext_interrupts=70
+	-firq
+	-interrupt_base=0x0
+	-dcache=65536,64,2,a
+	-dcache_feature=2
+	-dcache_uncached_region
+	-dcache_mem_cycles=2
+	-icache=65536,64,4,a
+	-icache_feature=2
+	-dccm_size=0x40000
+	-dccm_base=0x80000000
+	-dccm_mem_cycles=2
+	-iccm0_size=0x40000
+	-iccm0_base=0x70000000
+	-mpuv3
+	-mpu_regions=16
+	-noprofile
diff --git a/boards/arc/nsim/support/nsim_hs3x_hostlink.props b/boards/arc/nsim/support/nsim_hs3x_hostlink.props
@@ -0,0 +1,47 @@
+	nsim_isa_family=av2hs
+	nsim_isa_core=2
+	arcver=0x52
+	nsim_isa_rgf_num_banks=2
+	nsim_isa_rgf_banked_regs=32
+	nsim_isa_rgf_num_regs=32
+	nsim_isa_rgf_num_wr_ports=2
+	nsim_isa_big_endian=0
+	nsim_isa_lpc_size=32
+	nsim_isa_pc_size=32
+	nsim_isa_addr_size=32
+	nsim_isa_atomic_option=1
+	nsim_isa_ll64_option=1
+	nsim_isa_unaligned_option=1
+	nsim_isa_code_density_option=2
+	nsim_isa_div_rem_option=2
+	nsim_isa_swap_option=1
+	nsim_isa_bitscan_option=1
+	nsim_isa_mpy_option=9
+	nsim_isa_shift_option=3
+	nsim_isa_fpud_div_option=1
+	nsim_isa_fpu_mac_option=1
+	nsim_isa_enable_timer_0=1
+	nsim_isa_timer_0_int_level=1
+	nsim_isa_enable_timer_1=1
+	nsim_isa_timer_1_int_level=0
+	nsim_isa_rtc_option=1
+	nsim_isa_num_actionpoints=8
+	nsim_isa_stack_checking=1
+	nsim_isa_number_of_interrupts=72
+	nsim_isa_number_of_levels=2
+	nsim_isa_number_of_external_interrupts=70
+	nsim_isa_fast_irq=1
+	nsim_isa_intvbase_preset=0x0
+	dcache=65536,64,2,a
+	nsim_isa_dc_feature_level=2
+	nsim_isa_dc_uncached_region=1
+	nsim_isa_dc_mem_cycles=2
+	icache=65536,64,4,a
+	nsim_isa_ic_feature_level=2
+	dccm_size=0x40000
+	dccm_base=0x80000000
+	nsim_isa_dccm_mem_cycles=2
+	iccm0_size=0x40000
+	iccm0_base=0x70000000
+	mpu_regions=16
+	mpu_version=3
-Original file line number
+Diff line change
@@ Expand Up / @@ -4,6 +4,7 @@ @@
      */
     #include "nsim.dtsi"
+    #include "nsim-uart-ns16550.dtsi"
     / {
     	ici: intercore-interrupt-unit {
@@ Expand Down @@