🌊 Digital timing diagram rendering engine

simple hyperram controller

The UVM written in Python

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

32-bit 5-Stage Pipelined RISC V RV32I Core

This repository is compilation of basics of System Verilog Assertions in context of formal verification

AMBA AXI VIP

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical i…

riscv-ctb-challenge-meeeeet created by GitHub Classroom

Training Neural Networks using Analog circuits

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://www.vlsisystemdesign.com/advanced-physical-design-using-openla…