This an implementation of 32-bit MIPS-lite single-cycle with Verilog.
You can use ModelSim simulator in Windows or Icarus Verilog + GTKWave packages in Linux to develop and test the code.
Proseccor can execute 17 instructions which are add, sub, slt, and, or, nor, bne, blez, bltz, bgtz, bgez, jal, j, andi, addi, ori, jr.
The implementation details have been written in the report file and in the comments in the code.
Single-cycle datapath for processor added as Final_datapath.jpg