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support stacking memBackends
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mjleven committed Nov 11, 2016
1 parent 0f821d9 commit 8861425
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Showing 24 changed files with 152 additions and 56 deletions.
7 changes: 6 additions & 1 deletion src/sst/elements/memHierarchy/membackend/delayBuffer.cc
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Expand Up @@ -17,7 +17,7 @@
#include <sst_config.h>
#include <sst/core/link.h>
#include "membackend/delayBuffer.h"

#include "sst/elements/memHierarchy/util.h"

using namespace SST;
using namespace SST::MemHierarchy;
Expand All @@ -26,6 +26,7 @@ using namespace SST::MemHierarchy;
DelayBuffer::DelayBuffer(Component *comp, Params &params) : SimpleMemBackend(comp, params){

// Get parameters
fixupParams( params, "clock", "backend.clock" );

UnitAlgebra delay = params.find<UnitAlgebra>("request_delay", UnitAlgebra("0ns"));

Expand All @@ -39,6 +40,10 @@ DelayBuffer::DelayBuffer(Component *comp, Params &params) : SimpleMemBackend(com
backendParams.insert("mem_size", params.find<std::string>("mem_size"));
backend = dynamic_cast<SimpleMemBackend*>(loadSubComponent(backendName, backendParams));

MemBackend::NotifyFunctor_1<DelayBuffer,ReqId>* handler =
new MemBackend::NotifyFunctor_1<DelayBuffer,ReqId>( this, &DelayBuffer::handleMemResponse);
backend->setResponseHandler( handler );

// Set up self links
if (delay.getValue() != 0) {
delay_self_link = comp->configureSelfLink("DelaySelfLink", delay.toString(), new Event::Handler<DelayBuffer>(this, &DelayBuffer::handleNextRequest));
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4 changes: 4 additions & 0 deletions src/sst/elements/memHierarchy/membackend/delayBuffer.h
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Expand Up @@ -32,8 +32,12 @@ class DelayBuffer : public SimpleMemBackend {
void setup();
void finish();
void clock();
virtual const std::string& getClockFreq() { return backend->getClockFreq(); }

private:
void handleMemReponse( ReqId id ) {
SimpleMemBackend::handleMemResponse( id );
}
struct Req {
Req( ReqId id, Addr addr, bool isWrite, unsigned numBytes ) :
id(id), addr(addr), isWrite(isWrite), numBytes(numBytes)
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2 changes: 1 addition & 1 deletion src/sst/elements/memHierarchy/membackend/dramSimBackend.cc
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Expand Up @@ -87,5 +87,5 @@ void DRAMSimMemory::dramSimDone(unsigned int id, uint64_t addr, uint64_t clockcy
if(0 == reqs.size())
dramReqs.erase(addr);

getConvertor()->handleMemResponse(reqId);
handleMemResponse(reqId);
}
Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,6 @@ void FlashDIMMSimMemory::FlashDIMMSimDone(unsigned int id, uint64_t addr, uint64
if(0 == reqs.size())
dramReqs.erase(addr);

getConvertor()->handleMemResponse(req);
handleMemResponse(req);
pendingRequests--;
}
Original file line number Diff line number Diff line change
Expand Up @@ -365,7 +365,7 @@ void GOBLINHMCSimBackend::processResponses() {
owner->getCurrentSimTimeNano() - matchedReq->getStartTime());

// Pass back to the controller to be handled, HMC sim is finished with it
getConvertor()->handleMemResponse(matchedReq->getRequest());
handleMemResponse(matchedReq->getRequest());

// Clear element from our map, it has been processed so no longer needed
tag_req_map.erase(resp_tag);
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Expand Up @@ -29,6 +29,14 @@ using namespace SST::MemHierarchy;
#define Debug(level, fmt, ... )
#endif

HMCMemBackendConvertor::HMCMemBackendConvertor(Component *comp, Params &params) :
MemBackendConvertor(comp,params)
{
MemBackend::NotifyFunctor_2<HMCMemBackendConvertor,ReqId,uint32_t>* handler =
new MemBackend::NotifyFunctor_2<HMCMemBackendConvertor,ReqId,uint32_t>( this, &HMCMemBackendConvertor::handleMemResponse);
m_backend->setResponseHandler( handler );
}

bool HMCMemBackendConvertor::issue( MemReq *req ) {

MemEvent* event = req->getMemEvent();
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Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,7 @@ namespace MemHierarchy {
class HMCMemBackendConvertor : public MemBackendConvertor {

public:
HMCMemBackendConvertor(Component *comp, Params &params) :
MemBackendConvertor(comp,params) {}
HMCMemBackendConvertor(Component *comp, Params &params);

virtual bool issue( MemReq* req );
virtual void handleMemResponse( ReqId reqId, uint32_t flags ) {
Expand Down
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Expand Up @@ -77,5 +77,5 @@ void HybridSimMemory::hybridSimDone(unsigned int id, uint64_t addr, uint64_t clo
if(reqs.size() == 0)
dramReqs.erase(addr);

getConvertor()->handleMemResponse(req);
handleMemResponse(req);
}
80 changes: 66 additions & 14 deletions src/sst/elements/memHierarchy/membackend/memBackend.h
Original file line number Diff line number Diff line change
Expand Up @@ -34,11 +34,49 @@ namespace MemHierarchy {

class MemBackend : public SubComponent {
public:
class NotifyFunctorBase {
public:
virtual ~NotifyFunctorBase() {}
};

template < class T1, class A1, class TRetval = void >
class NotifyFunctor_1 : public NotifyFunctorBase {
private:
T1* m_obj;
TRetval ( T1::*m_fptr )( A1 );

public:
NotifyFunctor_1( T1* obj, TRetval (T1::*fptr)(A1) ) :
m_obj( obj ),
m_fptr( fptr )
{}

virtual TRetval operator()( A1 a1 ) {
return (*m_obj.*m_fptr)( a1 );
}
};

template < class T1, class A1, class A2, class TRetval = void >
class NotifyFunctor_2 : public NotifyFunctorBase {
private:
T1* m_obj;
TRetval ( T1::*m_fptr )( A1, A2 );

public:
NotifyFunctor_2( T1* obj, TRetval (T1::*fptr)(A1,A2) ) :
m_obj( obj ),
m_fptr( fptr )
{}

virtual TRetval operator()( A1 a1, A2 a2 ) {
return (*m_obj.*m_fptr)( a1, a2 );
}
};

typedef MemBackendConvertor::ReqId ReqId;
MemBackend();

MemBackend(Component *comp, Params &params) : SubComponent(comp), ctrl(NULL)
MemBackend(Component *comp, Params &params) : SubComponent(comp), m_handleMemResponse(NULL)
{
output = new SST::Output("@t:MemoryBackend[@p:@l]: ",
params.find<uint32_t>("debug_level", 0),
Expand Down Expand Up @@ -70,12 +108,17 @@ class MemBackend : public SubComponent {
delete output;
}

virtual void setConvertor( MemBackendConvertor* convertor ) {
ctrl = dynamic_cast<MemBackendConvertor*>(convertor);
if (!ctrl) {
output->fatal(CALL_INFO, -1, "MemBackends expect to be loaded into MemBackendConvertor.\n");
}
}
virtual void setResponseHandler( NotifyFunctorBase* functor ) {
m_handleMemResponse = functor;
}

virtual void setGetRequestorHandler( NotifyFunctor_1<MemBackendConvertor,ReqId,const std::string&>* functor ) {
m_getRequestor = functor;
}

std::string getRequestor( ReqId id ) {
return (*m_getRequestor)( id );
}

virtual void setup() {}
virtual void finish() {}
Expand All @@ -91,7 +134,8 @@ class MemBackend : public SubComponent {
size_t m_memSize;
int32_t m_reqWidth;

MemBackendConvertor *ctrl;
NotifyFunctorBase* m_handleMemResponse;
NotifyFunctor_1<MemBackendConvertor,ReqId,const std::string&>* m_getRequestor;
};

class SimpleMemBackend : public MemBackend {
Expand All @@ -100,18 +144,26 @@ class SimpleMemBackend : public MemBackend {
SimpleMemBackend(Component *comp, Params &params) : MemBackend(comp,params) {}

virtual bool issueRequest( ReqId, Addr, bool isWrite, unsigned numBytes ) = 0;
virtual SimpleMemBackendConvertor* getConvertor( ) {
return static_cast<SimpleMemBackendConvertor*>(ctrl);
};

void handleMemResponse( ReqId id ) {

NotifyFunctor_1< SimpleMemBackendConvertor,ReqId>* tmp;
tmp = static_cast< NotifyFunctor_1< SimpleMemBackendConvertor,ReqId>* >( m_handleMemResponse );
(*tmp)( id );
}
};

class HMCMemBackend : public MemBackend {
public:
HMCMemBackend(Component *comp, Params &params) : MemBackend(comp,params) {}
virtual bool issueRequest( ReqId, Addr, bool isWrite, uint32_t flags, unsigned numBytes ) = 0;
virtual HMCMemBackendConvertor* getConvertor( ) {
return static_cast<HMCMemBackendConvertor*>(ctrl);
};

void handleMemResponse( ReqId id, uint32_t flags ) {

NotifyFunctor_2< HMCMemBackendConvertor,ReqId,uint32_t>* tmp;
tmp = static_cast< NotifyFunctor_2< HMCMemBackendConvertor,ReqId,uint32_t>* >( m_handleMemResponse );
(*tmp)( id, flags );
}
};

}}
Expand Down
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Expand Up @@ -42,7 +42,12 @@ MemBackendConvertor::MemBackendConvertor(Component *comp, Params& params ) :
// extract backend parameters for memH.
Params backendParams = params.find_prefix_params("backend.");
m_backend = dynamic_cast<MemBackend*>( comp->loadSubComponent( backendName, comp, backendParams ) );
m_backend->setConvertor(this);

MemBackend::NotifyFunctor_1<MemBackendConvertor,ReqId,const std::string&>* functor;

functor = new MemBackend::NotifyFunctor_1<MemBackendConvertor,ReqId,const std::string&>( this, &MemBackendConvertor::getRequestor );

m_backend->setGetRequestorHandler( functor );

m_frontendRequestWidth = params.find<uint32_t>("request_width",64);
m_backendRequestWidth = static_cast<SimpleMemBackend*>(m_backend)->getRequestWidth();
Expand Down
7 changes: 3 additions & 4 deletions src/sst/elements/memHierarchy/membackend/pagedMultiBackend.cc
Original file line number Diff line number Diff line change
Expand Up @@ -369,7 +369,7 @@ bool pagedMultiMemory::issueRequest(ReqId id, Addr addr, bool isWrite, unsigned
SimTime_t extraDelay = 0;
auto &page = pageMap[pageAddr];

page.record(addr, isWrite, ctrl->getRequestor(id), collectStats, pageAddr, replaceStrat == LFU8);
page.record(addr, isWrite, getRequestor(id), collectStats, pageAddr, replaceStrat == LFU8);

if (maxFastPages > 0) {
if (modelSwaps && pageIsSwapping(page)) {
Expand Down Expand Up @@ -507,7 +507,7 @@ void pagedMultiMemory::handleSelfEvent(SST::Event *event){
delete ev;
} else {
// 'normal' event
getConvertor()->handleMemResponse(req->id);
handleMemResponse(req->id);
delete req;
delete event;
}
Expand Down Expand Up @@ -608,8 +608,7 @@ void pagedMultiMemory::dramSimDone(unsigned int id, uint64_t addr, uint64_t cloc
} else {
// normal request
assert(req);
assert(ctrl);
getConvertor()->handleMemResponse(req->id);
handleMemResponse(req->id);
delete req;
}
}
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -82,5 +82,5 @@ void ramulatorMemory::ramulatorDone(ramulator::Request& ramReq) {
if(0 == reqs.size())
dramReqs.erase(addr);

getConvertor()->handleMemResponse(req);
handleMemResponse(req);
}
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@ using namespace SST::MemHierarchy;

/*------------------------------- Simple Backend ------------------------------- */
RequestReorderRow::RequestReorderRow(Component *comp, Params &params) : SimpleMemBackend(comp, params){

fixupParams( params, "clock", "backend.clock" );

// Get parameters
reqsPerCycle = params.find<int>("max_requests_per_cycle", -1);
Expand Down Expand Up @@ -54,6 +56,9 @@ RequestReorderRow::RequestReorderRow(Component *comp, Params &params) : SimpleMe
Params backendParams = params.find_prefix_params("backend.");
backendParams.insert("mem_size", params.find<std::string>("mem_size"));
backend = dynamic_cast<SimpleMemBackend*>(loadSubComponent(backendName, backendParams));
MemBackend::NotifyFunctor_1<RequestReorderRow,ReqId>* handler =
new MemBackend::NotifyFunctor_1<RequestReorderRow,ReqId>( this, &RequestReorderRow::handleMemResponse);
backend->setResponseHandler( handler );

// Set up local variables
nextBank = 0;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,12 @@ class RequestReorderRow : public SimpleMemBackend {
void setup();
void finish();
void clock();
virtual const std::string& getClockFreq() { return backend->getClockFreq(); }

private:
void handleMemReponse( ReqId id ) {
SimpleMemBackend::handleMemResponse( id );
}
struct Req {
Req( ReqId id, Addr addr, bool isWrite, unsigned numBytes ) :
id(id), addr(addr), isWrite(isWrite), numBytes(numBytes)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,8 @@ using namespace SST::MemHierarchy;
/*------------------------------- Simple Backend ------------------------------- */
RequestReorderSimple::RequestReorderSimple(Component *comp, Params &params) : SimpleMemBackend(comp, params){

fixupParams( params, "clock", "backend.clock" );

reqsPerCycle = params.find<int>("max_requests_per_cycle", -1);
searchWindowSize = params.find<int>("search_window_size", -1);

Expand All @@ -32,6 +34,9 @@ RequestReorderSimple::RequestReorderSimple(Component *comp, Params &params) : Si
Params backendParams = params.find_prefix_params("backend.");
backendParams.insert("mem_size", params.find<std::string>("mem_size"));
backend = dynamic_cast<SimpleMemBackend*>(loadSubComponent(backendName, backendParams));
MemBackend::NotifyFunctor_1<RequestReorderSimple,ReqId>* handler =
new MemBackend::NotifyFunctor_1<RequestReorderSimple,ReqId>( this, &RequestReorderSimple::handleMemResponse);
backend->setResponseHandler( handler );
}

bool RequestReorderSimple::issueRequest(ReqId id, Addr addr, bool isWrite, unsigned numBytes ) {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,12 @@ class RequestReorderSimple : public SimpleMemBackend {
void setup();
void finish();
void clock();
virtual const std::string& getClockFreq() { return backend->getClockFreq(); }

private:
void handleMemReponse( ReqId id ) {
SimpleMemBackend::handleMemResponse( id );
}
struct Req {
Req( ReqId id, Addr addr, bool isWrite, unsigned numBytes ) :
id(id), addr(addr), isWrite(isWrite), numBytes(numBytes)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ void SimpleDRAM::handleSelfEvent(SST::Event *event){
} else {
busy[ev->bank] = false;
}
getConvertor()->handleMemResponse(ev->reqId);
handleMemResponse(ev->reqId);
delete event;
} else {
openRow[ev->bank] = -1;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ void SimpleMemory::handleSelfEvent(SST::Event *event){
#ifdef __SST_DEBUG_OUTPUT__
output->debug(_L10_, "%s: Transaction done for id %" PRIx64 "\n", parent->getName().c_str(),ev->reqId);
#endif
getConvertor()->handleMemResponse(ev->reqId);
handleMemResponse(ev->reqId);
delete event;
}

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,14 @@
using namespace SST;
using namespace SST::MemHierarchy;

bool SimpleMemBackendConvertor::issue( MemReq* req ) {
SimpleMemBackendConvertor::SimpleMemBackendConvertor(Component *comp, Params &params) :
MemBackendConvertor(comp,params)
{
MemBackend::NotifyFunctor_1<SimpleMemBackendConvertor,ReqId>* handler =
new MemBackend::NotifyFunctor_1<SimpleMemBackendConvertor,ReqId>( this, &SimpleMemBackendConvertor::handleMemResponse);
m_backend->setResponseHandler( handler );
}

bool SimpleMemBackendConvertor::issue( MemReq* req ) {
return static_cast<SimpleMemBackend*>(m_backend)->issueRequest( req->id(), req->addr(), req->isWrite(), m_backendRequestWidth );
}
Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,7 @@ class SimpleMemBackendConvertor : public MemBackendConvertor {


public:
SimpleMemBackendConvertor(Component *comp, Params &params) :
MemBackendConvertor(comp,params) {}
SimpleMemBackendConvertor(Component *comp, Params &params);

virtual bool issue( MemReq* req );

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -278,7 +278,7 @@ class TimingDRAM : public SimpleMemBackend {
virtual bool issueRequest( ReqId, Addr, bool, unsigned );
void handleResponse(ReqId id ) {
output->verbose(CALL_INFO, 2, DBG_MASK, "req=%p\n", id );
getConvertor()->handleMemResponse( id );
handleMemResponse( id );
}
virtual void clock();
virtual void finish() {}
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ void VaultSimMemory::handleCubeEvent(SST::Event *event){
if (ev) {
if ( outToCubes.find( ev->getReqId() ) != outToCubes.end() ) {
outToCubes.erase( ev->getReqId() );
getConvertor()->handleMemResponse( ev->getReqId(), ev->getFlags() );
handleMemResponse( ev->getReqId(), ev->getFlags() );
delete event;
} else {
output->fatal(CALL_INFO, -1, "Could not match incoming request from cubes\n");
Expand Down
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