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migrate C-extension opcodes (major)
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- the previous opcodes used ignore to define immediate fields instead of assigning arg names to it. This is made it difficult to parse and decode the instructions.
- this commit assigns unique names to immediate fields in accordance to what has been done elsewhere. Note these names hold no correspondence to the spec and are defined here purely to ease decoding
- This commit also splits the instructions which depend on F/D/Q in to their respective files as per new naming convention
- c.nop encoding has been changed to include hints as well.
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neelgala committed Apr 8, 2022
1 parent 56147c7 commit 88085a5
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Showing 9 changed files with 85 additions and 65 deletions.
5 changes: 0 additions & 5 deletions opcodes-rv32c

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14 changes: 0 additions & 14 deletions opcodes-rv64c

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46 changes: 0 additions & 46 deletions opcodes-rvc

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15 changes: 15 additions & 0 deletions rv128_c
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# quadrant 0
c.lq rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1
c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3
c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5
c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7

#quadrant 1
c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1

#quadrant 2
c.lqsp rd c_uimm10sphi c_uimm10splo 1..0=2 15..13=1
c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3
c.sqsp c_rs2 c_uimm10sp_s 1..0=2 15..13=5
c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7

5 changes: 5 additions & 0 deletions rv32_c
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# quadrant 1
c.jal c_imm12 1..0=1 15..13=1
$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0
$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1
$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0
8 changes: 8 additions & 0 deletions rv32_c_f
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# quadrant 0
c.flw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=3
c.fsw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=7

#quadrant 2
c.flwsp rd c_uimm8sphi c_uimm8splo 1..0=2 15..13=3
c.fswsp c_rs2 c_uimm8sp_s 1..0=2 15..13=7

17 changes: 17 additions & 0 deletions rv64_c
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# quadrant 0
c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3
c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7

#quadrant 1
c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1
c.srli rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=0
c.srai rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=1
c.subw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=0
c.addw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=1


#quadrant 2
c.slli rd_rs1_n0 c_nzuimm6hi c_nzuimm6lo 1..0=2 15..13=0
c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3
c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7

32 changes: 32 additions & 0 deletions rv_c
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# quadrant 0
c.addi4spn rd_p c_nzuimm10 1..0=0 15..13=0
c.lw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=2
c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=6

#quadrant 1
c.nop c_nzimm6hi c_nzimm6lo 1..0=1 15..13=0 11..7=0
c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi 1..0=1 15..13=0
c.li rd c_imm6lo c_imm6hi 1..0=1 15..13=2
c.addi16sp c_nzimm10hi c_nzimm10lo 1..0=1 15..13=3 11..7=2
c.lui rd_n2 c_nzimm18hi c_nzimm18lo 1..0=1 15..13=3
c.andi rd_rs1_p c_imm6hi c_imm6lo 1..0=1 15..13=4 11..10=2
c.sub rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=0
c.xor rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=1
c.or rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=2
c.and rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=3
c.j c_imm12 1..0=1 15..13=5
c.beqz rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=6
c.bnez rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=7

#quadrant 2
c.lwsp rd_n0 c_uimm8sphi c_uimm8splo 1..0=2 15..13=2
c.jr rs1_n0 1..0=2 15..13=4 12=0 6..2=0
c.mv rd c_rs2_n0 1..0=2 15..13=4 12=0
c.ebreak 1..0=2 15..13=4 12=1 11..2=0
c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0
c.add rd_rs1 c_rs2_n0 1..0=2 15..13=4 12=1
c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6




8 changes: 8 additions & 0 deletions rv_c_d
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#quadrant 0
c.fld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=1
c.fsd rs1_p rs2_p c_uimm8lo c_uimm8hi 1..0=0 15..13=5

#quadrant 2
c.fldsp rd c_uimm9sphi c_uimm9splo 1..0=2 15..13=1
c.fsdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=5

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