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Merge pull request hrydgard#7673 from unknownbrackets/ir-parts
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Merge in some parts of the jit IR stuff (not a lot)
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@hrydgard
hrydgard committed Apr 11, 2015
2 parents 106326f + 81dec36 commit 0bf4822
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Showing 25 changed files with 279 additions and 185 deletions.
60 changes: 30 additions & 30 deletions Core/MIPS/ARM/ArmCompBranch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -60,13 +60,13 @@ namespace MIPSComp
void ArmJit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
}
int offset = _IMM16 << 2;
MIPSGPReg rt = _RT;
MIPSGPReg rs = _RS;
u32 targetAddr = js.compilerPC + offset + 4;
u32 targetAddr = GetCompilerPC() + offset + 4;

bool immBranch = false;
bool immBranchTaken = false;
Expand Down Expand Up @@ -104,7 +104,7 @@ void ArmJit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)
return;
}

MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4);
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
CONDITIONAL_NICE_DELAYSLOT;

Expand All @@ -115,7 +115,7 @@ void ArmJit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)
else
FlushAll();

const u32 destAddr = immBranchTaken ? targetAddr : js.compilerPC + 8;
const u32 destAddr = immBranchTaken ? targetAddr : GetCompilerPC() + 8;
WriteExit(destAddr, js.nextExit++);
} else {
if (!likely && delaySlotIsNice)
Expand Down Expand Up @@ -163,7 +163,7 @@ void ArmJit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)

SetJumpTarget(ptr);
// Not taken
WriteExit(js.compilerPC + 8, js.nextExit++);
WriteExit(GetCompilerPC() + 8, js.nextExit++);
}

js.compiling = false;
Expand All @@ -173,12 +173,12 @@ void ArmJit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)
void ArmJit::BranchRSZeroComp(MIPSOpcode op, CCFlags cc, bool andLink, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
}
int offset = _IMM16 << 2;
MIPSGPReg rs = _RS;
u32 targetAddr = js.compilerPC + offset + 4;
u32 targetAddr = GetCompilerPC() + offset + 4;

bool immBranch = false;
bool immBranchTaken = false;
Expand Down Expand Up @@ -210,7 +210,7 @@ void ArmJit::BranchRSZeroComp(MIPSOpcode op, CCFlags cc, bool andLink, bool like
// Branch taken. Always compile the delay slot, and then go to dest.
CompileDelaySlot(DELAYSLOT_NICE);
if (andLink)
gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);

AddContinuedBlock(targetAddr);
// Account for the increment in the loop.
Expand All @@ -220,20 +220,20 @@ void ArmJit::BranchRSZeroComp(MIPSOpcode op, CCFlags cc, bool andLink, bool like
return;
}

MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
CONDITIONAL_NICE_DELAYSLOT;

if (immBranch) {
// Continuing is handled above, this is just static jumping.
if (immBranchTaken && andLink)
gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
if (immBranchTaken || !likely)
CompileDelaySlot(DELAYSLOT_FLUSH);
else
FlushAll();

const u32 destAddr = immBranchTaken ? targetAddr : js.compilerPC + 8;
const u32 destAddr = immBranchTaken ? targetAddr : GetCompilerPC() + 8;
WriteExit(destAddr, js.nextExit++);
} else {
if (!likely && delaySlotIsNice)
Expand Down Expand Up @@ -261,15 +261,15 @@ void ArmJit::BranchRSZeroComp(MIPSOpcode op, CCFlags cc, bool andLink, bool like
// Take the branch
if (andLink)
{
gpr.SetRegImm(SCRATCHREG1, js.compilerPC + 8);
gpr.SetRegImm(SCRATCHREG1, GetCompilerPC() + 8);
STR(SCRATCHREG1, CTXREG, MIPS_REG_RA * 4);
}

WriteExit(targetAddr, js.nextExit++);

SetJumpTarget(ptr);
// Not taken
WriteExit(js.compilerPC + 8, js.nextExit++);
WriteExit(GetCompilerPC() + 8, js.nextExit++);
}
js.compiling = false;
}
Expand Down Expand Up @@ -320,13 +320,13 @@ void ArmJit::Comp_RelBranchRI(MIPSOpcode op)
void ArmJit::BranchFPFlag(MIPSOpcode op, CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
}
int offset = _IMM16 << 2;
u32 targetAddr = js.compilerPC + offset + 4;
u32 targetAddr = GetCompilerPC() + offset + 4;

MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
CONDITIONAL_NICE_DELAYSLOT;
if (!likely && delaySlotIsNice)
Expand Down Expand Up @@ -356,7 +356,7 @@ void ArmJit::BranchFPFlag(MIPSOpcode op, CCFlags cc, bool likely)

SetJumpTarget(ptr);
// Not taken
WriteExit(js.compilerPC + 8, js.nextExit++);
WriteExit(GetCompilerPC() + 8, js.nextExit++);
js.compiling = false;
}

Expand All @@ -378,13 +378,13 @@ void ArmJit::Comp_FPUBranch(MIPSOpcode op)
void ArmJit::BranchVFPUFlag(MIPSOpcode op, CCFlags cc, bool likely)
{
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
}
int offset = _IMM16 << 2;
u32 targetAddr = js.compilerPC + offset + 4;
u32 targetAddr = GetCompilerPC() + offset + 4;

MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);

// Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
// The behavior is undefined - the CPU may take the second branch even if the first one passes.
Expand All @@ -395,7 +395,7 @@ void ArmJit::BranchVFPUFlag(MIPSOpcode op, CCFlags cc, bool likely)
if (!likely && delaySlotIsNice)
CompileDelaySlot(DELAYSLOT_NICE);
if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target", js.compilerPC);
ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target", GetCompilerPC());

int imm3 = (op >> 18) & 7;

Expand Down Expand Up @@ -426,7 +426,7 @@ void ArmJit::BranchVFPUFlag(MIPSOpcode op, CCFlags cc, bool likely)

SetJumpTarget(ptr);
// Not taken
u32 notTakenTarget = js.compilerPC + (delaySlotIsBranch ? 4 : 8);
u32 notTakenTarget = GetCompilerPC() + (delaySlotIsBranch ? 4 : 8);
WriteExit(notTakenTarget, js.nextExit++);
js.compiling = false;
}
Expand All @@ -444,11 +444,11 @@ void ArmJit::Comp_VBranch(MIPSOpcode op)

void ArmJit::Comp_Jump(MIPSOpcode op) {
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
}
u32 off = _IMM26 << 2;
u32 targetAddr = (js.compilerPC & 0xF0000000) | off;
u32 targetAddr = (GetCompilerPC() & 0xF0000000) | off;

// Might be a stubbed address or something?
if (!Memory::IsValidAddress(targetAddr)) {
Expand Down Expand Up @@ -480,7 +480,7 @@ void ArmJit::Comp_Jump(MIPSOpcode op) {
if (ReplaceJalTo(targetAddr))
return;

gpr.SetImm(MIPS_REG_RA, js.compilerPC + 8);
gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
CompileDelaySlot(DELAYSLOT_NICE);
if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions) {
AddContinuedBlock(targetAddr);
Expand All @@ -504,14 +504,14 @@ void ArmJit::Comp_Jump(MIPSOpcode op) {
void ArmJit::Comp_JumpReg(MIPSOpcode op)
{
if (js.inDelaySlot) {
ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
return;
}
MIPSGPReg rs = _RS;
MIPSGPReg rd = _RD;
bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;

MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
if (andLink && rs == rd)
delaySlotIsNice = false;
Expand All @@ -522,12 +522,12 @@ void ArmJit::Comp_JumpReg(MIPSOpcode op)
gpr.MapReg(rs);
MovToPC(gpr.R(rs)); // For syscall to be able to return.
if (andLink)
gpr.SetImm(rd, js.compilerPC + 8);
gpr.SetImm(rd, GetCompilerPC() + 8);
CompileDelaySlot(DELAYSLOT_FLUSH);
return; // Syscall wrote exit code.
} else if (delaySlotIsNice) {
if (andLink)
gpr.SetImm(rd, js.compilerPC + 8);
gpr.SetImm(rd, GetCompilerPC() + 8);
CompileDelaySlot(DELAYSLOT_NICE);

if (!andLink && rs == MIPS_REG_RA && g_Config.bDiscardRegsOnJRRA) {
Expand Down Expand Up @@ -559,7 +559,7 @@ void ArmJit::Comp_JumpReg(MIPSOpcode op)
gpr.MapReg(rs);
MOV(R8, gpr.R(rs));
if (andLink)
gpr.SetImm(rd, js.compilerPC + 8);
gpr.SetImm(rd, GetCompilerPC() + 8);
CompileDelaySlot(DELAYSLOT_NICE);
FlushAll();
}
Expand Down
2 changes: 1 addition & 1 deletion Core/MIPS/ARM/ArmCompFPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ void ArmJit::Comp_FPU3op(MIPSOpcode op)
case 0: VADD(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add
case 1: VSUB(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub
case 2: { //F(fd) = F(fs) * F(ft); //mul
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
MIPSOpcode nextOp = GetOffsetInstruction(1);
// Optimization possible if destination is the same
if (fd == (int)((nextOp>>6) & 0x1F)) {
// VMUL + VNEG -> VNMUL
Expand Down
2 changes: 1 addition & 1 deletion Core/MIPS/ARM/ArmCompLoadStore.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ namespace MIPSComp
if (!js.inDelaySlot) {
// Optimisation: Combine to single unaligned load/store
bool isLeft = (o == 34 || o == 42);
MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4);
MIPSOpcode nextOp = GetOffsetInstruction(1);
// Find a matching shift in opposite direction with opposite offset.
if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3)
: (op.encoding - (4<<26) + 3)))
Expand Down
4 changes: 2 additions & 2 deletions Core/MIPS/ARM/ArmCompVFPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,7 @@ namespace MIPSComp
// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
// TODO: But some ops seem to use const 0 instead?
if (regnum >= n) {
WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, js.compilerPC, MIPSDisasmAt(js.compilerPC));
WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(js.compilerPC));
regnum = 0;
}

Expand Down Expand Up @@ -2028,7 +2028,7 @@ namespace MIPSComp
u8 dregs[4];
u8 dregs2[4];

u32 nextOp = Memory::Read_Opcode_JIT(js.compilerPC + 4).encoding;
u32 nextOp = GetOffsetInstruction(1).encoding;
int vd2 = -1;
int imm2 = -1;
if ((nextOp >> 26) == 60 && ((nextOp >> 21) & 0x1F) == 29 && _VS == MIPS_GET_VS(nextOp)) {
Expand Down
12 changes: 6 additions & 6 deletions Core/MIPS/ARM/ArmCompVFPUNEON.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -284,9 +284,9 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
// Check for four-in-a-row
const u32 ops[4] = {
op.encoding,
Memory::Read_Instruction(js.compilerPC + 4).encoding,
Memory::Read_Instruction(js.compilerPC + 8).encoding,
Memory::Read_Instruction(js.compilerPC + 12).encoding
GetOffsetInstruction(1).encoding,
GetOffsetInstruction(2).encoding,
GetOffsetInstruction(3).encoding
};
if (g_Config.bFastMemory && (ops[1] >> 26) == 54 && (ops[2] >> 26) == 54 && (ops[3] >> 26) == 54) {
int offsets[4] = {offset, (s16)(ops[1] & 0xFFFC), (s16)(ops[2] & 0xFFFC), (s16)(ops[3] & 0xFFFC)};
Expand Down Expand Up @@ -350,9 +350,9 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
{
const u32 ops[4] = {
op.encoding,
Memory::Read_Instruction(js.compilerPC + 4).encoding,
Memory::Read_Instruction(js.compilerPC + 8).encoding,
Memory::Read_Instruction(js.compilerPC + 12).encoding
GetOffsetInstruction(1).encoding,
GetOffsetInstruction(2).encoding,
GetOffsetInstruction(3).encoding
};
if (g_Config.bFastMemory && (ops[1] >> 26) == 54 && (ops[2] >> 26) == 54 && (ops[3] >> 26) == 54) {
int offsets[4] = { offset, (s16)(ops[1] & 0xFFFC), (s16)(ops[2] & 0xFFFC), (s16)(ops[3] & 0xFFFC) };
Expand Down
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