target-mips: Streamline indexed cp1 memory addressing.

We've already eliminated both base and index being zero. Signed-off-by: Aurelien Jarno <[email protected]> (cherry picked from commit 0516867) Signed-off-by: Michael Roth <[email protected]>
milksleisure · Aug 28, 2012 · 2f0f684 · 2f0f684
1 parent bc4321e
commit 2f0f684
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/target-mips/translate.c b/target-mips/translate.c
@@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     } else if (index == 0) {
         gen_load_gpr(t0, base);
     } else {
-        gen_load_gpr(t0, index);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */