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A simple network quantization demo using pytorch from scratch.

Python 521 98 Updated Jun 18, 2023

The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

Verilog 121 17 Updated May 21, 2023

Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)

Python 10 3 Updated Feb 15, 2022

Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)

Verilog 11 4 Updated Jan 29, 2021

A small Neural Network Processor for Edge devices.

Verilog 7 2 Updated Nov 22, 2022

A curated list of Computer Architecture and Systems resources

488 53 Updated Dec 24, 2024
SystemVerilog 1 1 Updated May 2, 2023

Final project NOC for EE552

SystemVerilog 3 Updated Jul 30, 2023

EE552 Asynchronous VLSI Design, Prof Peter A. Beerel, Co-Author Daya Chou

SystemVerilog 4 Updated Sep 30, 2022
SystemVerilog 1 Updated May 13, 2023

Hardware and software implementation of Sparsely-active SNNs

SystemVerilog 11 4 Updated Jan 9, 2025

Asynchronous Spiking Neural Network Accelerator. Project from EE552-Asynchronous VLSI Design.

SystemVerilog 1 Updated Jun 17, 2023

Spiking Neural Network Accelerator

SystemVerilog 13 4 Updated May 18, 2022

Individual Study in Computer Architecture and Systems Laboratory (CASYS) with Prof.Jaehyuk Huh in 2021 Summer

Jupyter Notebook 4 Updated Jan 19, 2022

关于深度学习算法、框架、编译器、加速器的一些理解

14 1 Updated Jul 2, 2022

A CNN accelerator based on Eyeriss architecture

Verilog 4 Updated Jan 23, 2024

Deep Learning Accelerator (Convolution Neural Networks)

Verilog 170 61 Updated Dec 15, 2017

An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"

Python 184 51 Updated Dec 22, 2020

Convolutional accelerator kernel, target ASIC & FPGA

Verilog 178 29 Updated Apr 10, 2023
Verilog 9 Updated Jan 31, 2023

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Verilog 92 10 Updated Jan 31, 2025

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

Verilog 135 11 Updated Nov 3, 2024

Research and Materials on Hardware implementation of Transformer Model

Jupyter Notebook 229 35 Updated Feb 10, 2025

My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, Cheng Du, China. For more informantion about me and my resea…

43 9 Updated Feb 7, 2023

Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"

Python 11 4 Updated Apr 20, 2023

🧑‍🏫 60+ Implementations/tutorials of deep learning papers with side-by-side notes 📝; including transformers (original, xl, switch, feedback, vit, ...), optimizers (adam, adabelief, sophia, ...), ga…

Python 58,488 5,953 Updated Aug 24, 2024

Example code for Understanding Computation

Ruby 496 100 Updated Jul 6, 2015

Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.

154 15 Updated Nov 4, 2023

A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.

138 39 Updated Nov 16, 2017
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