arch/x86: (Intel64) clear BSS before entering long mode

This is really just to facilitate CPU bootstrap code between the BSP and the APs, moving the clear operation out of the way. Signed-off-by: Charles E. Youse <[email protected]>
mlaz · Oct 7, 2019 · 17e135b · 17e135b
1 parent a981f51
commit 17e135b
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diff --git a/arch/x86/core/intel64/locore.S b/arch/x86/core/intel64/locore.S
@@ -31,6 +31,17 @@ __start:
 	movw %ax, %fs
 	movw %ax, %gs
 
+	/*
+	 * clear the BSS. note that we do this in 32-bit mode, so
+	 * the BSS must fit entirely in the first 4GB of RAM.
+	 */
+
+	cld
+	xorl %eax, %eax
+	movl $__bss_start, %edi
+	movl $__bss_num_dwords, %ecx
+	rep stosl
+
 	movl $(_interrupt_stack + CONFIG_ISR_STACK_SIZE), %esp
 
 	/* transition to long mode. along the way, we enable SSE. */
@@ -67,11 +78,7 @@ __start:
 	movl $X86_KERNEL_GS_64, %eax
 	movw %ax, %gs
 
-	cld
-	xorl %eax, %eax
-	movq $__bss_start, %rdi
-	movq $__bss_num_qwords, %rcx
-	rep stosq
+	movl $(_interrupt_stack + CONFIG_ISR_STACK_SIZE), %esp
 
 #ifdef CONFIG_INIT_STACKS
 	movq $0xAAAAAAAAAAAAAAAA, %rax

diff --git a/include/arch/x86/intel64/linker.ld b/include/arch/x86/intel64/linker.ld
@@ -87,11 +87,11 @@ SECTIONS
 	*(.bss)
 	*(.bss.*)
 	*(COMMON)
-	. = ALIGN(8);	/* so __bss_num_qwords is exact */
+	. = ALIGN(4);	/* so __bss_num_dwords is exact */
 	__bss_end = .;
 	} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
-	__bss_num_qwords = (__bss_end - __bss_start) >> 3;
+	__bss_num_dwords = (__bss_end - __bss_start) >> 2;
 
 	SECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD), ALIGN(16))
 	{