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board: olimex_stm32_e407: fix default 48MHz clock divisor
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The previously used default value of 4 for the PPL_Q_DIVISOR results
in a frequency of 84MHz which is outside the acceptable range
of 47.88MHz to 48.12MHz.

The new value of 7 results in exactly 48MHz.

Signed-off-by: Erwin Rol <[email protected]>
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@lowlander @galak
lowlander authored and galak committed Aug 2, 2017
1 parent d7c32cf commit 36ddd47
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=6
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=168
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=4
CONFIG_CLOCK_STM32_APB2_PRESCALER=2
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