arch: kinetis: Add support for k2x

This adds support for Kinestis K22 Co-authored-by: Sean Nyekjaer <[email protected]> Co-authored-by: Oliver Stäbler <[email protected]> Co-authored-by: Tom Burdick <[email protected]> Signed-off-by: Tom Burdick <[email protected]>
mlaz · Sep 25, 2019 · 6a708e6 · 6a708e6
1 parent 78170ec
commit 6a708e6
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diff --git a/dts/arm/nxp/nxp_k2x.dtsi b/dts/arm/nxp/nxp_k2x.dtsi
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2018 Prevas A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/kinetis_sim.h>
+#include <dt-bindings/clock/kinetis_mcg.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
+	 * contiguous block in the memory map, however misaligned accesses
+	 * across the 0x2000_0000 boundary are not supported in the Arm
+	 * Cortex-M4 architecture. For clarity and to avoid the temptation for
+	 * someone to extend sram0 without solving this issue, we define two
+	 * separate memory nodes here and only use the upper one for now. A
+	 * potential solution has been proposed in binutils:
+	 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
+	 */
+	sram_l: memory@1fff0000 {
+		compatible = "mmio-sram";
+		reg = <0x1fff0000 0x10000>;
+	};
+
+	sram0: memory@20000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x10000>;
+	};
+
+	soc {
+
+		mpu@4000d000 {
+			compatible = "nxp,k22f-mpu";
+			reg = <0x4000d000 0x824>;
+
+			status = "disabled";
+		};
+
+		mcg: clock-controller@40064000 {
+			compatible = "nxp,k22f-mcg";
+			reg = <0x40064000 0xd>;
+			system-clock-frequency = <120000000>;
+
+			clock-controller;
+		};
+
+		clock-controller@40065000 {
+			compatible = "nxp,k22f-osc";
+			reg = <0x40065000 0x4>;
+
+			enable-external-reference;
+		};
+
+		rtc@4003d000 {
+			compatible = "nxp,k22f-rtc";
+			reg = <0x4003d000 0x808>;
+			clock-frequency = <32768>;
+		};
+
+		sim: sim@40047000 {
+			compatible = "nxp,kinetis-sim";
+			reg = <0x40047000 0x1060>;
+			label = "SIM";
+
+			#clock-cells = <3>;
+		};
+
+		flash-controller@40020000 {
+			compatible = "nxp,kinetis-ftfe";
+			label = "FLASH_CTRL";
+			reg = <0x40020000 0x18>;
+			interrupts = <18 0>, <19 0>;
+			interrupt-names = "command-complete", "read-collision";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				label = "MCUX_FLASH";
+				reg = <0 0x100000>;
+				erase-block-size = <2048>;
+				write-block-size = <8>;
+			};
+		};
+
+		i2c0: i2c@40066000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40066000 0x1000>;
+			interrupts = <24 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
+			label = "I2C_0";
+			status = "disabled";
+		};
+
+		i2c1: i2c@40067000 {
+			compatible = "nxp,kinetis-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40067000 0x1000>;
+			interrupts = <25 0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
+			label = "I2C_1";
+			status = "disabled";
+		};
+
+		uart0: uart@4006a000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006a000 0x1000>;
+			interrupts = <31 0>, <32 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
+			label = "UART_0";
+
+			pinctrl-0 = <&uart0_default>;
+			pinctrl-names = "default";
+
+			status = "disabled";
+		};
+
+		uart1: uart@4006b000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006b000 0x1000>;
+			interrupts = <33 0>, <34 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+
+		uart2: uart@4006c000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006c000 0x1000>;
+			interrupts = <35 0>, <36 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
+			label = "UART_2";
+
+			status = "disabled";
+		};
+
+		uart3: uart@4006d000 {
+			compatible = "nxp,kinetis-uart";
+			reg = <0x4006d000 0x1000>;
+			interrupts = <37 0>, <38 0>;
+			interrupt-names = "status", "error";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
+			label = "UART_3";
+
+			status = "disabled";
+		};
+
+		pinmux_a: pinmux@40049000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x40049000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
+		};
+
+		pinmux_b: pinmux@4004a000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004a000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
+		};
+
+		pinmux_c: pinmux@4004b000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004b000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
+		};
+
+		pinmux_d: pinmux@4004c000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004c000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
+
+			spi0_default: spi0_default {
+				miso-mosi-clk {
+					pins = <1>, <2>, <3>;
+					function = <2>;
+				};
+			};
+		};
+
+		pinmux_e: pinmux@4004d000 {
+			compatible = "nxp,kinetis-pinmux";
+			reg = <0x4004d000 0xd0>;
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
+
+			uart0_default: uart0_default {
+				rx-tx {
+					pins = <0>, <1>;
+					function = <3>;
+				};
+			};
+		};
+
+		gpioa: gpio@400ff000 {
+			compatible = "nxp,kinetis-gpio";
+			reg = <0x400ff000 0x40>;
+			interrupts = <59 2>;
+			label = "GPIO_0";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpiob: gpio@400ff040 {
+			compatible = "nxp,kinetis-gpio";
+			reg = <0x400ff040 0x40>;
+			interrupts = <60 2>;
+			label = "GPIO_1";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpioc: gpio@400ff080 {
+			compatible = "nxp,kinetis-gpio";
+			reg = <0x400ff080 0x40>;
+			interrupts = <61 2>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpiod: gpio@400ff0c0 {
+			compatible = "nxp,kinetis-gpio";
+			reg = <0x400ff0c0 0x40>;
+			interrupts = <62 2>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpioe: gpio@400ff100 {
+			compatible = "nxp,kinetis-gpio";
+			reg = <0x400ff100 0x40>;
+			interrupts = <63 2>;
+			label = "GPIO_4";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		spi0: spi@4002c000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x4002c000 0x88>;
+			interrupts = <26 3>;
+			label = "SPI_0";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pinctrl-0 = <&spi0_default>;
+			pinctrl-names = "default";
+		};
+
+		spi1: spi@4002d000 {
+			compatible = "nxp,kinetis-dspi";
+			reg = <0x4002d000 0x88>;
+			interrupts = <27 3>;
+			label = "SPI_1";
+			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		wdog: watchdog@40052000 {
+			compatible = "nxp,kinetis-wdog";
+			reg = <0x40052000 16>;
+			interrupts = <22 0>;
+			clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
+			label = "WDT_0";
+		};
+
+		pwm0: pwm@40038000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x40038000 0x98>;
+			interrupts = <42 0>;
+			label = "PWM_0";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm1: pwm@40039000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x40039000 0x98>;
+			interrupts = <43 0>;
+			label = "PWM_1";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm2: pwm@4003a000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x4003a000 0x98>;
+			interrupts = <44 0>;
+			label = "PWM_2";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm3: pwm@400b9000{
+			compatible = "nxp,kinetis-ftm";
+			reg = <0x400b9000 0x98>;
+			interrupts = <71 0>;
+			label = "PWM_3";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		adc0: adc@4003b000{
+			compatible = "nxp,kinetis-adc16";
+			reg = <0x4003b000 0x70>;
+			interrupts = <39 0>;
+			label = "ADC_0";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		usbd: usbd@40072000 {
+			compatible = "nxp,kinetis-usbd";
+			reg = <0x40072000 0x1000>;
+			interrupts = <53 1>;
+			interrupt-names = "usb_otg";
+			num-bidir-endpoints = <16>;
+			status = "disabled";
+			label = "USBD";
+		};
+
+		rnga: random@40029000 {
+			compatible = "nxp,kinetis-rnga";
+			reg = <0x40029000 0x1000>;
+			status = "okay";
+			interrupts = <23 0>;
+			label = "RNGA";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux
@@ -147,4 +147,9 @@ config HAS_MCUX_PWM
 	help
 	  Set if the PWM  module is present in the SoC.
 
+config HAS_MCUX_SMC
+	bool
+	help
+	  Set if the SMC  module is present in the SoC.
+
 endif # HAS_MCUX
diff --git a/soc/arm/nxp_kinetis/Kconfig b/soc/arm/nxp_kinetis/Kconfig
@@ -19,6 +19,7 @@ source "soc/arm/nxp_kinetis/*/Kconfig.soc"
 
 config SOC_PART_NUMBER
 	string
+	default SOC_PART_NUMBER_KINETIS_K2X if SOC_SERIES_KINETIS_K2X
 	default SOC_PART_NUMBER_KINETIS_K6X if SOC_SERIES_KINETIS_K6X
 	default SOC_PART_NUMBER_KINETIS_K8X if SOC_SERIES_KINETIS_K8X
 	default SOC_PART_NUMBER_KINETIS_KWX if SOC_SERIES_KINETIS_KWX

diff --git a/soc/arm/nxp_kinetis/k2x/CMakeLists.txt b/soc/arm/nxp_kinetis/k2x/CMakeLists.txt
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2018 Prevas A/S
+
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(
+  soc.c
+  wdog.S
+  )