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ssb: update reject bit for Target State Low
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My 14e4:4315 is SSB_IDLOW_SSBREV_26:
read32 0xfaafcff8 -> 0x600422d5
My 14e4:4328 is SSB_IDLOW_SSBREV_24:
read32 0xfaafcff8 -> 0x400422c5
My 14e4:432b is SSB_IDLOW_SSBREV_26 again:
read32 0xfaafcff8 -> 0x600422d5

For all of them wl driver is using 0x2 reject bit:
write32(0xf98) <- 0x00010002
So it seems SSB 2.3 is the exception using another bit.

Signed-off-by: Rafał Miłecki <[email protected]>
Signed-off-by: John W. Linville <[email protected]>
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rmilecki authored and linvjw committed Apr 26, 2011
1 parent a6ef814 commit 04ad1fb
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Showing 2 changed files with 8 additions and 9 deletions.
15 changes: 7 additions & 8 deletions drivers/ssb/main.c
Original file line number Diff line number Diff line change
Expand Up @@ -1117,23 +1117,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
{
u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;

/* The REJECT bit changed position in TMSLOW between
* Backplane revisions. */
/* The REJECT bit seems to be different for Backplane rev 2.3 */
switch (rev) {
case SSB_IDLOW_SSBREV_22:
return SSB_TMSLOW_REJECT_22;
case SSB_IDLOW_SSBREV_24:
case SSB_IDLOW_SSBREV_26:
return SSB_TMSLOW_REJECT;
case SSB_IDLOW_SSBREV_23:
return SSB_TMSLOW_REJECT_23;
case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
case SSB_IDLOW_SSBREV_25: /* same here */
case SSB_IDLOW_SSBREV_26: /* same here */
case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
case SSB_IDLOW_SSBREV_27: /* same here */
return SSB_TMSLOW_REJECT_23; /* this is a guess */
return SSB_TMSLOW_REJECT; /* this is a guess */
default:
printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
WARN_ON(1);
}
return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
}

int ssb_device_is_enabled(struct ssb_device *dev)
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2 changes: 1 addition & 1 deletion include/linux/ssb/ssb_regs.h
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@
#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
#define SSB_TMSLOW 0x0F98 /* SB Target State Low */
#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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