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Merge tag 'gvt-fixes-2019-06-19' of https://github.com/intel/gvt-linux
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…into drm-intel-fixes

gvt-fixes-2019-06-19

- Fix reserved PVINFO register write (Weinan)

Signed-off-by: Jani Nikula <[email protected]>
From: Zhenyu Wang <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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jnikula committed Jun 19, 2019
2 parents 9e0babf + 971afec commit f5633ef
Showing 1 changed file with 9 additions and 6 deletions.
15 changes: 9 additions & 6 deletions drivers/gpu/drm/i915/gvt/handlers.c
Original file line number Diff line number Diff line change
Expand Up @@ -1254,18 +1254,15 @@ static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
u32 data;
int ret;

write_vreg(vgpu, offset, p_data, bytes);
data = vgpu_vreg(vgpu, offset);
u32 data = *(u32 *)p_data;
bool invalid_write = false;

switch (offset) {
case _vgtif_reg(display_ready):
send_display_ready_uevent(vgpu, data ? 1 : 0);
break;
case _vgtif_reg(g2v_notify):
ret = handle_g2v_notification(vgpu, data);
handle_g2v_notification(vgpu, data);
break;
/* add xhot and yhot to handled list to avoid error log */
case _vgtif_reg(cursor_x_hot):
Expand All @@ -1282,13 +1279,19 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
case _vgtif_reg(execlist_context_descriptor_hi):
break;
case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
invalid_write = true;
enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
break;
default:
invalid_write = true;
gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
offset, bytes, data);
break;
}

if (!invalid_write)
write_vreg(vgpu, offset, p_data, bytes);

return 0;
}

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