rdfremont: configure system counter implementation defined registers

On RD-Fremont and variant platforms, the system counter should increment at 1GHz as per SBSA requirement. With the refclk at 125Mhz, these platforms require a per-tick system counter increment of 8. This increment value has to be programmed in the implementation defined registers of system counter control register frame. So provide the table of impdef register offsets and its corresponding values in the gtimer module config data. It is SCP firmware that configures the system counter register frame and so the table is supplied as config data to only the SCP firmware. For the MCP firmware, update the system counter increment frequency as 1GHz. Signed-off-by: Thomas Abraham <[email protected]> Change-Id: Ibda329735f9ac9df61434b2b5aafabd69da956da
mohamedasaker-arm · Jan 28, 2024 · 39858a0 · 39858a0
1 parent 69b8cc1
commit 39858a0
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Showing 3 changed files with 21 additions and 3 deletions.
diff --git a/product/neoverse-rd/rdfremont/mcp_ramfw/config_gtimer.c b/product/neoverse-rd/rdfremont/mcp_ramfw/config_gtimer.c
@@ -31,7 +31,7 @@ static const struct fwk_element gtimer_dev_table[MOD_GTIMER_ELEMENT_COUNT]  = {
                 .hw_timer = MCP_REFCLK_CNTBASE0_BASE,
                 .hw_counter = MCP_REFCLK_CNTCTL_BASE,
                 .control = MCP_REFCLK_CNTCONTROL_BASE,
-                .frequency = CLOCK_RATE_REFCLK,
+                .frequency = (CLOCK_RATE_REFCLK * SYSCNT_INCR),
                 .clock_id = FWK_ID_NONE_INIT,
                 .skip_cntcontrol_init = true }),
     },

diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/CMakeLists.txt b/product/neoverse-rd/rdfremont/scp_ramfw/CMakeLists.txt
@@ -16,7 +16,8 @@ add_executable(rdfremont-bl2)
 target_include_directories(
     rdfremont-bl2
     PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/include"
-           "${CMAKE_CURRENT_SOURCE_DIR}/../include")
+           "${CMAKE_CURRENT_SOURCE_DIR}/../include"
+           "${CMAKE_CURRENT_SOURCE_DIR}/../../common/include")
 
 target_sources(
     rdfremont-bl2

diff --git a/product/neoverse-rd/rdfremont/scp_ramfw/config_gtimer.c b/product/neoverse-rd/rdfremont/scp_ramfw/config_gtimer.c
@@ -10,6 +10,7 @@
 
 #include "scp_clock.h"
 #include "scp_css_mmap.h"
+#include "syscnt_impdef.h"
 
 #include <mod_gtimer.h>
 
@@ -22,15 +23,31 @@
 /* Module 'gtimer' element count */
 #define MOD_GTIMER_ELEMENT_COUNT 2
 
+/*
+ * System counter implementation defined register config data.
+ */
+static struct mod_gtimer_syscounter_impdef_config syscnt_impdef_cfg[] = {
+    {
+        .offset = NEOVERSE_RD_SYSCNT_IMPDEF0_CNTENCR,
+        .value = 0,
+    },
+    {
+        .offset = NEOVERSE_RD_SYSCNT_IMPDEF0_CNTINCR,
+        .value = SYSCNT_INCR,
+    }
+};
+
 /* Generic timer driver config */
 static const struct fwk_element gtimer_dev_table[MOD_GTIMER_ELEMENT_COUNT] = {
     [0] = { .name = "REFCLK",
             .data = &((struct mod_gtimer_dev_config){
                 .hw_timer = SCP_REFCLK_CNTBASE0_BASE,
                 .hw_counter = SCP_REFCLK_CNTCTL_BASE,
                 .control = SCP_REFCLK_CNTCONTROL_BASE,
-                .frequency = CLOCK_RATE_REFCLK,
+                .frequency = (CLOCK_RATE_REFCLK * SYSCNT_INCR),
                 .clock_id = FWK_ID_NONE_INIT,
+                .syscnt_impdef_cfg = syscnt_impdef_cfg,
+                .syscnt_impdef_cfg_cnt = FWK_ARRAY_SIZE(syscnt_impdef_cfg),
             }) },
     [1] = { 0 },
 };