rdn2: configure system counter implementation defined registers

On RD-N2 and variant platforms, the system counter should increment at 1GHz as per SBSA requirement. With the refclk at 125Mhz, these platforms require a per-tick system counter increment of 8. This increment value has to be programmed in the implementation defined registers of system counter control register frame. So provide the table of impdef register offsets and its corresponding values in the gtimer module config data. It is SCP firmware that configures the system counter register frame and so the table is supplied as config data to only the SCP firmware. For the MCP firmware, update the system counter increment frequency as 1GHz. Signed-off-by: Thomas Abraham <[email protected]> Change-Id: I1a1a1562d7dbd5a06ec6adcca1a6e9c1f75f878b
mohamedasaker-arm · Jan 28, 2024 · d508371 · d508371
1 parent d997fcb
commit d508371
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Showing 4 changed files with 27 additions and 6 deletions.
diff --git a/product/neoverse-rd/rdn2/include/clock_soc.h b/product/neoverse-rd/rdn2/include/clock_soc.h
@@ -14,6 +14,9 @@
 
 #define CLOCK_RATE_REFCLK (125UL * FWK_MHZ)
 
+/* System Counter per-tick increment value */
+#define SYSCNT_INCR 8
+
 #define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
 
 #if (PLATFORM_VARIANT == 3)

diff --git a/product/neoverse-rd/rdn2/mcp_ramfw/config_gtimer.c b/product/neoverse-rd/rdn2/mcp_ramfw/config_gtimer.c
@@ -1,6 +1,6 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,7 +25,7 @@ static const struct fwk_element gtimer_dev_table[] = {
                 .hw_timer = MCP_REFCLK_CNTBASE0_BASE,
                 .hw_counter = MCP_REFCLK_CNTCTL_BASE,
                 .control = MCP_REFCLK_CNTCONTROL_BASE,
-                .frequency = CLOCK_RATE_REFCLK,
+                .frequency = (CLOCK_RATE_REFCLK * SYSCNT_INCR),
                 .clock_id = FWK_ID_NONE_INIT,
                 .skip_cntcontrol_init = true }), },
     [1] = { 0 },

diff --git a/product/neoverse-rd/rdn2/scp_ramfw/CMakeLists.txt b/product/neoverse-rd/rdn2/scp_ramfw/CMakeLists.txt
@@ -1,6 +1,6 @@
 #
 # Arm SCP/MCP Software
-# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -40,7 +40,8 @@ endif()
 
 target_include_directories(
     rdn2-bl2 PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/../include"
-                    "${CMAKE_CURRENT_SOURCE_DIR}")
+                    "${CMAKE_CURRENT_SOURCE_DIR}"
+                    "${CMAKE_CURRENT_SOURCE_DIR}/../../common/include")
 
 # cmake-lint: disable=E1122
 

diff --git a/product/neoverse-rd/rdn2/scp_ramfw/config_gtimer.c b/product/neoverse-rd/rdn2/scp_ramfw/config_gtimer.c
@@ -1,12 +1,13 @@
 /*
  * Arm SCP/MCP Software
- * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "clock_soc.h"
 #include "scp_css_mmap.h"
+#include "syscnt_impdef.h"
 
 #include <mod_gtimer.h>
 
@@ -16,6 +17,20 @@
 #include <fwk_module_idx.h>
 #include <fwk_time.h>
 
+/*
+ * System counter implementation defined register config data.
+ */
+static struct mod_gtimer_syscounter_impdef_config syscnt_impdef_cfg[] = {
+    {
+        .offset = NEOVERSE_RD_SYSCNT_IMPDEF0_CNTENCR,
+        .value = 0,
+    },
+    {
+        .offset = NEOVERSE_RD_SYSCNT_IMPDEF0_CNTINCR,
+        .value = SYSCNT_INCR,
+    }
+};
+
 /*
  * Generic timer driver config
  */
@@ -25,8 +40,10 @@ static const struct fwk_element gtimer_dev_table[] = {
                 .hw_timer = SCP_REFCLK_CNTBASE0_BASE,
                 .hw_counter = SCP_REFCLK_CNTCTL_BASE,
                 .control = SCP_REFCLK_CNTCONTROL_BASE,
-                .frequency = CLOCK_RATE_REFCLK,
+                .frequency = (CLOCK_RATE_REFCLK * SYSCNT_INCR),
                 .clock_id = FWK_ID_NONE_INIT,
+                .syscnt_impdef_cfg = syscnt_impdef_cfg,
+                .syscnt_impdef_cfg_cnt = FWK_ARRAY_SIZE(syscnt_impdef_cfg),
             }) },
     [1] = { 0 },
 };