A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Collection of various algorithms in mathematics, machine learning, computer science and physics implemented in C++ for educational purposes.

SystemC - design and testbench examples

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equ…

Reference examples and short projects using UVM Methodology

Contains the code examples from The UVM Primer Book sorted by chapters.

Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

Coverts a generic Verilog netlist into the DIMACS format compatible with many SAT solvers

UVM examples and projects

The code convert test bench file (.bench) to Verilog (.v) file.

Curvature Scale Space in Python