Basic RISC-V Test SoC

Design source of APB_UART, based on AMBA 3.0.

reference block design for the ASAP7nm library in Cadence Innovus

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

lowRISC Style Guides

Curriculum for a university course to teach chip design using open source EDA tools

This script builds openlane and all its dependencies on an Ubuntu (only) System.

This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components i…

ASIC Design of the openSPARC Floating Point Unit

RISC-V Linux SoC, marchID: 0x2b

A minimal GPU design in Verilog to learn how GPUs work from the ground up

An open source standard cell library using TIGFET 10nm devices.

CORE-V Family of RISC-V Cores

Software developer resume in Latex

Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, st…

An FPGA-based Chess Engine and TPU

FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de10-nano)

Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

Learning FPGA, yosys, nextpnr, and RISC-V

A Verilog RTL implementation of a Master/Slave Serial Peripheral Interface Block

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Advanced encryption standard implementation in verilog.