fix bugs

moonbeam87 · Sep 2, 2017 · 621a3a8 · 621a3a8
1 parent d847aae
commit 621a3a8
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Showing 5 changed files with 33 additions and 15 deletions.
diff --git a/cpp/accel/Accel.h b/cpp/accel/Accel.h
@@ -10,14 +10,14 @@
 #include "Debug.h"
 #include "Common.h"
 
-#ifdef __SDSCC__
+/*#ifdef __SDSCC__
   #include "sds_lib.h"
   #define MEM_ALLOC(size) sds_alloc(size)
   #define MEM_FREE(ptr) sds_free(ptr)
 #else
   #define MEM_ALLOC(size) malloc(size)
   #define MEM_FREE(ptr) free(ptr)
-#endif
+#endif*/
 
 //-------------------------------------------------------------------
 // Constants

diff --git a/cpp/accel/Dense.cpp b/cpp/accel/Dense.cpp
@@ -18,15 +18,15 @@ DATA sigmoid(
   const DATA in
   ) {
   DATA out;
-  out = 1/(1+exp(-in));
+  out = 1/(1+hls::exp((ap_fixed<16,8>) in));
   return out;
 }
 
 DATA tanh(
   const DATA in
   ) {
   DATA out;
-  out = (exp(in) - exp(-in)) / (exp(in) + exp(-in));
+  out = (hls::exp((ap_fixed<16,8>) in) - hls::exp((ap_fixed<16,8>) -in)) / (hls::exp((ap_fixed<16,8>) in) + hls::exp((ap_fixed<16,8>) -in));
   return out;
 }
 
@@ -39,6 +39,7 @@ DATA dotproduct_m(
 ) {
   assert (M % WORD_SIZE == 0);
   DATA sum = 0;
+  static Word wt_wrd;
 
   // Loop across in the inputs in batches of WORD_SIZE
   for (unsigned m = 0; m < M; m+=WORD_SIZE) {
@@ -50,7 +51,7 @@ DATA dotproduct_m(
       in_wrd[i+2](15,0) = in[(m + i)/4](47,32);
       in_wrd[i+3](15,0) = in[(m + i)/4](63,48);
     }
-    const Word wt_wrd = w[(n*M+m)/WORD_SIZE];
+    wt_wrd = w[(n*M+m)/WORD_SIZE];
 
     for (unsigned i = 0; i < WORD_SIZE; ++i) {
       if (wt_wrd[i] > 0)
@@ -89,8 +90,8 @@ void dense_layer(
   //ap_uint<1> d_i_idx = dmem_mode;
   //ap_uint<1> d_o_idx = ~dmem_mode;
 
-  Word in[(M+N)/DATA_PER_WORD];
-  DATA gate[4][N];  // ML: input, forget, cell(tanh), output
+  static Word in[2*HID_SIZE/DATA_PER_WORD];
+  static DATA gate[4][HID_SIZE];  // ML: input, forget, cell(tanh), output
 
   if (layer_idx < 2) {
     LOOP_DMEM_I:
@@ -118,8 +119,8 @@ void dense_layer(
     }
   }
 
-  static Word* wt_i = (Word*) MEM_ALLOC( WT_WORDS*sizeof(Word));
-  static Word* b_i = (Word*) MEM_ALLOC( BIAS_WORDS*sizeof(Word));
+  static Word wt_i[WT_WORDS] = {0};
+  static Word b_i[BIAS_WORDS] = {0};
 
   LOOP_WT_I:
   for (unsigned j = 0; j < WT_WORDS; ++j)
@@ -180,7 +181,7 @@ void dense_layer(
       }
     }
 
-    LOOP_DMEM
+    LOOP_DMEM:
     for (unsigned n = 0; n < N; n++) {
       DATA cell;
       DATA cell_pre;

diff --git a/cpp/accel/Dense.h b/cpp/accel/Dense.h
@@ -17,14 +17,22 @@
     const unsigned M,
     const unsigned N
 );*/
+#ifdef __SDSCC__
+  #include "sds_lib.h"
+  #define MEM_ALLOC(size) sds_alloc(size)
+  #define MEM_FREE(ptr) sds_free(ptr)
+#else
+  #define MEM_ALLOC(size) malloc(size)
+  #define MEM_FREE(ptr) free(ptr)
+#endif
 
 #pragma SDS data copy(data_i[0:input_words], data_o[0:output_words])
 #pragma SDS data access_pattern(data_i:SEQUENTIAL, data_o:SEQUENTIAL)
 #pragma SDS data mem_attribute(data_i:PHYSICAL_CONTIGUOUS, data_o:PHYSICAL_CONTIGUOUS)
 #pragma SDS data data_mover(data_i:AXIDMA_SIMPLE, data_o:AXIDMA_SIMPLE)
-#pragma SDS data access_pattern(s[0].wt:SEQUENTIAL, s[0].b:SEQUENTIAL)
-#pragma SDS data mem_attribute(s[0].wt:PHYSICAL_CONTIGUOUS, s[0].b:PHYSICAL_CONTIGUOUS)
-#pragma SDS data data_mover(s[0].wt:AXIDMA_SIMPLE, s[0].b:AXIDMA_SIMPLE)
+//#pragma SDS data access_pattern(s[0].wt:SEQUENTIAL, s[0].b:SEQUENTIAL)
+//#pragma SDS data mem_attribute(s[0].wt:PHYSICAL_CONTIGUOUS, s[0].b:PHYSICAL_CONTIGUOUS)
+//#pragma SDS data data_mover(s[0].wt:AXIDMA_SIMPLE, s[0].b:AXIDMA_SIMPLE)
 void dense_layer(
     const Word* data_i,
     Word* data_o,

diff --git a/cpp/accel/sdsoc_build/sds.tcl b/cpp/accel/sdsoc_build/sds.tcl
@@ -1,8 +1,8 @@
 set rootdir $::env(CRAFT_BNN_ROOT)
 source $rootdir/cpp/accel/opt.tcl
 
-set_directive_interface -mode ap_fifo "dense_layer" s[0].wt
-set_directive_interface -mode ap_fifo "dense_layer" s[0].b
+#set_directive_interface -mode ap_fifo "dense_layer" s[0].wt
+#set_directive_interface -mode ap_fifo "dense_layer" s[0].b
 set_directive_interface -mode ap_fifo "dense_layer" data_i
 set_directive_interface -mode ap_fifo "dense_layer" data_o
 

diff --git a/settings64.sh b/settings64.sh
@@ -0,0 +1,9 @@
+##############################################################
+# Copyright (c) 1986-2017 Xilinx, Inc.  All rights reserved. #
+##############################################################
+
+source /home/hang/Xilinx/SDx/2017.1/SDK/.settings64-Software_Development_Kit.sh
+source /home/hang/Xilinx/DocNav/.settings64-DocNav.sh
+source /home/hang/Xilinx/SDx/2017.1/.settings64-SDx.sh
+source /home/hang/Xilinx/SDx/2017.1/Vivado_HLS/.settings64-SDx_High_Level_Synthesis.sh
+source /home/hang/Xilinx/SDx/2017.1/Vivado/.settings64-Vivado.sh