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fix: update string interpolation
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@peter-jerry-ye
peter-jerry-ye committed Aug 30, 2024
1 parent ac791a9 commit 063c3a6
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Showing 4 changed files with 60 additions and 60 deletions.
18 changes: 9 additions & 9 deletions lib/cartridge.mbt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,17 +36,17 @@ struct iNESHeader {

fn readiNESHeader(self : MemoryReader) -> iNESHeader {
let magic = self.readIntLE()
println("magic: \(magic)")
println("magic: \{magic})")
let numPRG = self.readUInt8()
let numCHR = self.readUInt8()
println("numPRG: \(numPRG)")
println("numCHR: \(numCHR)")
println("numPRG: \{numPRG})")
println("numCHR: \{numCHR})")
let control1 = self.readUInt8()
let control2 = self.readUInt8()
let numRAM = self.readUInt8()
println("control1: \(control1)")
println("control2: \(control2)")
println("numRAM: \(numRAM)")
println("control1: \{control1})")
println("control2: \{control2})")
println("numRAM: \{numRAM})")
let padding = self.readUInt8Array(7)
{ magic, numPRG, numCHR, control1, control2, numRAM, padding }
}
Expand Down Expand Up @@ -77,7 +77,7 @@ fn newCartridge(data : FixedArray[Int]) -> Cartridge {
let mapper1 = header.control1.lsr(4)
let mapper2 = header.control2.lsr(4)
let mapper = mapper1.lor(mapper2.lsl(4))
println("mapper: \(mapper)")
println("mapper: \{mapper})")

// mirroring type
let mirror1 = header.control1.land(1 |> to_u8)
Expand All @@ -98,14 +98,14 @@ fn newCartridge(data : FixedArray[Int]) -> Cartridge {

// read prg-rom bank(s)
let prg = reader.readUInt8Array(prg_len)
println("read \(prg_len) bytes of prg-rom")
println("read \{prg_len} bytes of prg-rom")

// read chr-rom bank(s)
// provide chr-rom/ram if not in file
let chr = if header.numCHR == (0 |> to_u8) {
FixedArray::make(8192, 0 |> to_u8)
} else {
println("read \(chr_len) bytes of chr-rom")
println("read \{chr_len} bytes of chr-rom")
reader.readUInt8Array(chr_len)
}
let sram = FixedArray::make(0x2000, 0 |> to_u8)
Expand Down
78 changes: 39 additions & 39 deletions lib/cpu.mbt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
let cpuFrequency = 1789773.0

struct CPUMemory {
mut nes : Option[NES] // Emulating "weakptr"
mut nes : NES? // Emulating "weakptr"
}

fn CPUMemory::new() -> CPUMemory {
Expand Down Expand Up @@ -142,7 +142,9 @@ fn op_set(self : CPUMemory, adr : UInt16, val : UInt8) -> Unit {
n.ppu.writeRegister((0x2000 |> to_u16) + (adr.0 % 8 |> to_u16), val)
} else if adr.0 == 0x4014 {
n.ppu.writeRegister(adr, val)
} else if adr.0 >= 0x4000 && adr.0 <= 0x4013 || adr.0 == 0x4015 || adr.0 == 0x4017 {
} else if (adr.0 >= 0x4000 && adr.0 <= 0x4013) ||
adr.0 == 0x4015 ||
adr.0 == 0x4017 {
n.apu.writeRegister(adr, val)
} else if adr.0 == 0x4016 {
n.controllers[0].write(val)
Expand All @@ -162,9 +164,9 @@ fn read16(self : CPUMemory, adr : UInt16) -> UInt16 {
fn read16bug(self : CPUMemory, adr : UInt16) -> UInt16 {
// Low byte wraps without incrementing high byte
let a = adr
let b = a.land(0xFF00 |> to_u16).lor(
(adr |> to_u8()) + (1 |> to_u8()) |> to_u16,
)
let b = a
.land(0xFF00 |> to_u16)
.lor((adr |> to_u8()) + (1 |> to_u8()) |> to_u16)
let lo = self[a]
let hi = self[b]
(hi |> to_u16).lsl(8).lor(lo |> to_u16)
Expand Down Expand Up @@ -275,26 +277,26 @@ fn formatAssemblySuffix(self : CPU) -> String {
let address = self.mem[self.pc + (1 |> to_u16)]
let address_hex = address.to_hex()
match mode {
Immediate => "#$\(address_hex)"
ZeroPage => "$\(mem_addr8_hex) = \(stored_value_hex)"
Immediate => "#$\{address_hex}"
ZeroPage => "$\{mem_addr8_hex} = \{stored_value_hex}"
ZeroPageX =>
"$\(address_hex),X @ \(mem_addr8_hex) = \(stored_value_hex)"
"$\{address_hex},X @ \{mem_addr8_hex} = \{stored_value_hex}"
ZeroPageY =>
"$\(address_hex),Y @ \(mem_addr8_hex) = \(stored_value_hex)"
"$\{address_hex},Y @ \{mem_addr8_hex} = \{stored_value_hex}"
// Indirect_X
IndexedIndirect => {
let new_addr_hex = (address + self.x).to_hex()
"($\(address_hex),X) @ \(new_addr_hex) = \(mem_addr_hex) = \(stored_value_hex)"
"($\{address_hex},X) @ \{new_addr_hex} = \{mem_addr_hex} = \{stored_value_hex}"
}
// Indirect_Y
IndirectIndexed => {
// sub???
let new_addr_hex = (mem_addr - (self.y |> to_u16)).to_hex() // 16-bit
"($\(address_hex)),Y = \(new_addr_hex) @ \(mem_addr_hex) = \(stored_value_hex)"
"($\{address_hex}),Y = \{new_addr_hex} @ \{mem_addr_hex} = \{stored_value_hex}"
}
Relative =>
// assuming local jumps: BNE, BVS, etc....
"$\(mem_addr_hex)"
"$\{mem_addr_hex}"
//_ => abort("unexpected addressing mode {:?} has ops-len 2. code {:02x}")
_ => ""
}
Expand All @@ -306,7 +308,7 @@ fn formatAssemblySuffix(self : CPU) -> String {
let address = self.mem.read16(self.pc + (1 |> to_u16))
let address_hex = address.to_hex()
match mode {
Indirect => "($\(address_hex)) = \(mem_addr_hex)"
Indirect => "($\{address_hex}) = \{mem_addr_hex}"
Relative =>
// if opcode.0 == 0x6c {
// //jmp indirect
Expand All @@ -323,15 +325,15 @@ fn formatAssemblySuffix(self : CPU) -> String {
// } else {
// format!("${:04x}", address)
// }
"$\(address_hex)"
"$\{address_hex}"
Absolute =>
if name == "JMP" || name == "JSR" {
"$\(address_hex)"
"$\{address_hex}"
} else {
"$\(mem_addr_hex) = \(stored_value_hex)"
"$\{mem_addr_hex} = \{stored_value_hex}"
}
AbsoluteX => "$\(address_hex),X @ \(mem_addr_hex) = \(stored_value_hex)"
AbsoluteY => "$\(address_hex),Y @ \(mem_addr_hex) = \(stored_value_hex)"
AbsoluteX => "$\{address_hex},X @ \{mem_addr_hex} = \{stored_value_hex}"
AbsoluteY => "$\{address_hex},Y @ \{mem_addr_hex} = \{stored_value_hex}"
//_ => abort("unexpected addressing mode {:?} has ops-len 3. code {:02x}",
_ => ""
}
Expand Down Expand Up @@ -374,7 +376,7 @@ fn formatInstruction(self : CPU) -> String {
let y = self.y.to_hex()
let p = self.flags().to_hex()
let sp = self.sp.to_hex()
"\(pc) \(w0) \(w1) \(w2) \(uf)\(asm)A:\(a) X:\(x) Y:\(y) P:\(p) SP:\(sp)"
"\{pc} \{w0} \{w1} \{w2} \{uf}\{asm}A:\{a} X:\{x} Y:\{y} P:\{p} SP:\{sp}"
}

// Mesen2's trace logger format：everything except "use labels" and "indent based on stack pointer"
Expand Down Expand Up @@ -403,7 +405,7 @@ fn formatInstructionWithMesen2Extended(self : CPU) -> String {
let y = self.y.to_hex()
let p = self.flags().to_hex()
let sp = self.sp.to_hex()
"\(pc) \(w0) \(w1) \(w2) \(uf)\(asm)A:\(a) X:\(x) Y:\(y) P:\(p) SP:\(sp)"
"\{pc} \{w0} \{w1} \{w2} \{uf}\{asm}A:\{a} X:\{x} Y:\{y} P:\{p} SP:\{sp}"
}

fn formatMemoryDump(self : CPU, base : UInt16, cnt : Int) -> String {
Expand Down Expand Up @@ -474,9 +476,8 @@ fn opADC(self : CPU, info : StepInfo) -> Unit {
self.setZN(self.a)
self.c = a.0 + b.0 + c.0 > 0xFF
// (a^b)&0x80 == 0 && (a^self.a)&0x80 != 0
self.v = a.lxor(b).land(0x80 |> to_u8()) == (0 |> to_u8()) && a.lxor(self.a).land(
0x80 |> to_u8(),
) != (0 |> to_u8())
self.v = a.lxor(b).land(0x80 |> to_u8()) == (0 |> to_u8()) &&
a.lxor(self.a).land(0x80 |> to_u8()) != (0 |> to_u8())
}

// AND - Logical and
Expand Down Expand Up @@ -795,9 +796,8 @@ fn opSBC(self : CPU, info : StepInfo) -> Unit {
self.a = a - b - ((1 |> to_u8()) - c)
self.setZN(self.a)
self.c = a.0 - b.0 - ((1 |> to_u8()) - c).0 >= 0
self.v = a.lxor(b).land(0x80 |> to_u8()) != (0 |> to_u8()) && a.lxor(self.a).land(
0x80 |> to_u8(),
) != (0 |> to_u8())
self.v = a.lxor(b).land(0x80 |> to_u8()) != (0 |> to_u8()) &&
a.lxor(self.a).land(0x80 |> to_u8()) != (0 |> to_u8())
}

// SEC - Set carry flag
Expand Down Expand Up @@ -1011,7 +1011,7 @@ let instructions: FixedArray[(CPU, StepInfo) -> Unit] = [ // All 6502 instructio
opCPX, opSBC, opNOP, opISC, opCPX, opSBC, opINC, opISC,//E
opINX, opSBC, opNOP, opSBC, opCPX, opSBC, opINC, opISC,
opBEQ, opSBC, opKIL, opISC, opNOP, opSBC, opINC, opISC,//F
opSED, opSBC, opNOP, opISC, opNOP, opSBC, opINC, opISC,
opSED, opSBC, opNOP, opISC, opNOP, opSBC, opINC, opISC,
]

// instructionNames indicates the name of each instruction
Expand Down Expand Up @@ -1068,7 +1068,7 @@ let
9, 8, 5, 8, 11, 11, 11, 11, 5, 2, 5, 2, 1, 1, 1, 1,
4, 6, 4, 6, 10, 10, 10, 10, 5, 4, 5, 4, 0, 0, 0, 0,
9, 8, 5, 8, 11, 11, 11, 11, 5, 2, 5, 2, 1, 1, 1, 1,
]
]

let
instructionSizes: FixedArray[Int] = [ // Size in bytes
Expand All @@ -1088,7 +1088,7 @@ let
2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 1, 3, 3, 3, 3, 3,
2, 2, 0, 2, 2, 2, 2, 2, 1, 2, 1, 2, 3, 3, 3, 3,
2, 2, 0, 2, 2, 2, 2, 2, 1, 3, 1, 3, 3, 3, 3, 3,
]
]

let
instructionCycles: FixedArray[Int] = [ // Number of cycles used
Expand All @@ -1108,7 +1108,7 @@ let
2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,
2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6,
2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7,
]
]

let
instructionPageCycles: FixedArray[Int] = [ // Cycles used on a page cross
Expand All @@ -1128,7 +1128,7 @@ let
1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0,
]
]

let
instructionUnofficial: FixedArray[Int] = [ // 1 if official
Expand All @@ -1149,7 +1149,7 @@ let
0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 1,//D
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1,//E
0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 1,//F
]
]


// Non-maskable interrupt
Expand Down Expand Up @@ -1186,8 +1186,8 @@ fn get_addr(self : CPU, mode : AddressingMode) -> UInt16 {
self.mem.read16bug(self.mem[self.pc + (1 |> to_u16)] + self.x |> to_u16)
Indirect => self.mem.read16bug(self.mem.read16(self.pc + (1 |> to_u16)))
IndirectIndexed =>
self.mem.read16bug(self.mem[self.pc + (1 |> to_u16)] |> to_u16) + (self.y
|> to_u16)
self.mem.read16bug(self.mem[self.pc + (1 |> to_u16)] |> to_u16) +
(self.y |> to_u16)
ZeroPage => self.mem[self.pc + (1 |> to_u16)] |> to_u16
ZeroPageX => self.mem[self.pc + (1 |> to_u16)] + self.x |> to_u16 // CHECKME
ZeroPageY => self.mem[self.pc + (1 |> to_u16)] + self.y |> to_u16
Expand Down Expand Up @@ -1234,11 +1234,11 @@ fn step(self : CPU, trace_log : Bool) -> Int {
let adr = self.get_addr(mode)

// CHECKME: AbsoluteX can cross page too!
if mode == AbsoluteX && pagesDiffer(adr - (self.x |> to_u16), adr) || (
[AbsoluteY, IndirectIndexed] : FixedArray[AddressingMode]).contains(mode) && pagesDiffer(
adr - (self.y |> to_u16),
adr,
) {
if (mode == AbsoluteX && pagesDiffer(adr - (self.x |> to_u16), adr)) ||
(
([AbsoluteY, IndirectIndexed] : FixedArray[AddressingMode]).contains(mode) &&
pagesDiffer(adr - (self.y |> to_u16), adr)
) {
self.cycles += instructionPageCycles[opcode.0].to_int64()
}
self.pc += instructionSizes[opcode.0] |> to_u16
Expand Down
22 changes: 11 additions & 11 deletions lib/mapper.mbt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,7 @@ fn idxSet(self : Mapper2, adr : UInt16, val : UInt8) -> Unit {
fn Mapper2::new(cartridge : Cartridge) -> Mapper2 {
let prg_len = cartridge.prg.length()
let prgBanks = prg_len / 0x4000
println("Mapper2::new: \(prg_len) \(prgBanks)")
println("Mapper2::new: \{prg_len} \{prgBanks}")
{ cartridge, prgBanks, prgBank1: 0, prgBank2: prgBanks - 1 }
}

Expand All @@ -123,12 +123,12 @@ fn to_string(self : Mapper2) -> String {
let prgBanks = self.prgBanks
let prgBank1 = self.prgBank1
let prgBank2 = self.prgBank2
"\(prg_len) \(prgBanks) \(prgBank1) \(prgBank2)"
"\{prg_len} \{prgBanks} \{prgBank1} \{prgBank2}"
}

fn newMapper2(self : NES) -> Mapper {
let mapper = Mapper2::new(self.cartridge)
println("mapper: \(mapper)")
println("mapper: \{mapper}")
to_mapper(mapper)
}

Expand Down Expand Up @@ -246,8 +246,8 @@ fn writePRGBank(self : Mapper1, value : UInt8) -> Unit {
}

fn prgBankOffset(self : Mapper1, index : Int) -> Int {
let index = if index >= 0x80 { index - 0x100 } else { index } % (self.cartridge.prg.length() /
0x4000)
let index = if index >= 0x80 { index - 0x100 } else { index } %
(self.cartridge.prg.length() / 0x4000)
let offset = index * 0x4000
if offset < 0 {
offset + self.cartridge.prg.length()
Expand All @@ -257,8 +257,8 @@ fn prgBankOffset(self : Mapper1, index : Int) -> Int {
}

fn chrBankOffset(self : Mapper1, index : Int) -> Int {
let index = if index >= 0x80 { index - 0x100 } else { index } % (self.cartridge.chr.length() /
0x1000)
let index = if index >= 0x80 { index - 0x100 } else { index } %
(self.cartridge.chr.length() / 0x1000)
let offset = index * 0x1000
if offset < 0 {
offset + self.cartridge.chr.length()
Expand Down Expand Up @@ -517,8 +517,8 @@ fn writeIRQEnable(self : Mapper4, value : UInt8) -> Unit {
}

fn prgBankOffset(self : Mapper4, index : Int) -> Int {
let index = if index >= 0x80 { index - 0x100 } else { index } % (self.cartridge.prg.length() /
0x2000)
let index = if index >= 0x80 { index - 0x100 } else { index } %
(self.cartridge.prg.length() / 0x2000)
let offset = index * 0x2000
if offset < 0 {
offset + self.cartridge.prg.length()
Expand All @@ -528,8 +528,8 @@ fn prgBankOffset(self : Mapper4, index : Int) -> Int {
}

fn chrBankOffset(self : Mapper4, index : Int) -> Int {
let index = if index >= 0x80 { index - 0x100 } else { index } % (self.cartridge.chr.length() /
0x0400)
let index = if index >= 0x80 { index - 0x100 } else { index } %
(self.cartridge.chr.length() / 0x0400)
let offset = index * 0x0400
if offset < 0 {
offset + self.cartridge.chr.length()
Expand Down
2 changes: 1 addition & 1 deletion lib/nes.mbt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ fn formatCycleInfo(self : NES) -> String {
let ppu_x = self.ppu.scanLine |> formatInt3()
let ppu_y = self.ppu.cycle |> formatInt3()
let cyc = self.cpu.cycles
"PPU:\(ppu_x),\(ppu_y) CYC:\(cyc)"
"PPU:\{ppu_x},\{ppu_y} CYC:\{cyc}"
}

pub fn nestest(rom : FixedArray[Int]) -> Unit {
Expand Down

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