Update to mempool configuration

based on pulp-platform/mempool/commit/82639303ea9266e601cbd228a0f540648d78061e

Makefile

@@ -1,29 +1,39 @@
 SHELL := /bin/sh
 
-ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom
+ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system
+ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv
+# Add here your opcodes
+MY_OPCODES := opcodes-frep_CUSTOM opcodes-xpulpimg_CUSTOM opcodes-rv32d-zfh_DRAFT opcodes-rv32q-zfh_DRAFT opcodes-rv32zfh_DRAFT opcodes-rv64zfh_DRAFT opcodes_sflt_CUSTOM
 
+ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) $(MY_OPCODES) opcodes-rvv-pseudo
+# Opcodes to be discarded
+DISCARDED_OPCODES := opcodes-frep_CUSTOM
 
-inst.chisel: $(ALL_OPCODES) parse-opcodes
-	cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -chisel > $@
+OPCODES = $(filter-out $(sort $(DISCARDED_OPCODES)), $(sort $(ALL_OPCODES)))
 
-inst.go: opcodes opcodes-pseudo parse-opcodes
-	cat opcodes opcodes-pseudo opcodes-pulp | ./parse-opcodes -go > $@
+all: encoding_out.h inst.sverilog
 
-inst.c: opcodes opcodes-pseudo parse-opcodes
-	cat opcodes opcodes-pseudo opcodes-pulp | ./parse-opcodes -c > $@
+# Makefile inserted as prerequisite of every recipe because it can change due to DISCARDED_OPCODES
 
-inst.sv: opcodes opcodes-pseudo parse-opcodes
-	cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-pseudo opcodes-pulp | ./parse-opcodes -sv > $@
+encoding_out.h: $(OPCODES) parse_opcodes encoding.h Makefile
+	echo "/*" > $@
+	echo " * This file is auto-generated by running 'make $@' in 'riscv-opcodes'" >> $@
+	echo " */" >> $@
+	echo >> $@
+	cat encoding.h >> $@
+	cat $(OPCODES) | ./parse_opcodes -c >> $@
 
-inst.py: opcodes opcodes-pseudo parse-opcodes
-	cat opcodes opcodes-pseudo opcodes-pulp | ./parse-opcodes -py > $@
+inst.chisel: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES) | ./parse_opcodes -chisel > $@
 
+inst.go: $(ALL_REAL_ILEN32_OPCODES) parse_opcodes Makefile
+	cat $(ALL_REAL_ILEN32_OPCODES) | ./parse_opcodes -go > $@
 
-inst.sverilog: opcodes opcodes-pseudo parse-opcodes
-	cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -sverilog > $@
+inst.sverilog: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES) | ./parse_opcodes -sverilog > $@
 
-instr-table.tex: $(ALL_OPCODES) parse-opcodes
-	cat opcodes opcodes-pseudo opcodes-pulp | ./parse-opcodes -tex > $@
+instr-table.tex: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES) | ./parse_opcodes -tex > $@
 
-priv-instr-table.tex: $(ALL_OPCODES) parse-opcodes
-	cat opcodes opcodes-pseudo | ./parse-opcodes -privtex > $@
+priv-instr-table.tex: $(OPCODES) parse_opcodes Makefile
+	cat $(OPCODES) | ./parse_opcodes -privtex > $@

README.md

@@ -1,7 +1,39 @@
 riscv-opcodes
 ===========================================================================
 
-This repo enumerates standard RISC-V instruction opcodes, control and status
-registers and PULP specific instruction opcodes. It also contains a script to
-convert them into several formats (C, Python, Go, Scala, SystemVerilog LaTeX).
-Functions will be instantiated to decode those instructions.
+This repo enumerates standard RISC-V instruction opcodes and control and
+status registers, as well as some custom modifications.  It also contains a
+script to convert them into several formats (C, SystemVerilog, Scala, LaTeX),
+starting from their high-level, human-readable description.
+
+## Practical info
+- Every output of the parser is generated inside this folder; tools which
+  need such automatically generated files must use soft link to point to them.
+  For example, supposing `RISCV_ISA_SIM_TOOL` is set to the source code directory of
+  the Spike simulator:
+
+  ```bash
+  ln -sfr encoding_out.h $RISCV_ISA_SIM_TOOL/encoding.h
+  ```
+
+  Example of where the outputs of `parse-opcodes` are used in other projects
+
+  | Parser output  | Destination                                    |
+  |:--------------:|:-----------------------------------------------|
+  | encoding_out.h | riscv-gnu-toolchain/riscv-binutils-gdb/include/opcode/riscv-opc.h <br> riscv-isa-sim/riscv/encoding.h <br> riscv-pk/machine/encoding.h <br> riscv-tests/env/encoding.h <br> riscv-openocd/src/target/riscv/encoding.h <br> _custom use_ i.e. apps/common/encoding.h |
+  | inst.sverilog  | snitch/src/riscv_instr.sv |
+
+- opcodes description files organization matches the same of the official
+  repository upstream [riscv-opcodes](https://github.com/riscv/riscv-opcodes),
+  with the addition of several custom instruction set extensions: you can
+  add your own custom extensions as text file in the root, subsequently
+  adding it to the variable `MY_OPCODES` of the `Makefile`
+- in the `Makefile`, you can select which opcodes files not to take into account
+  for the parsing script execution, basing on the target architecture, by
+  listing them in the variable `DISCARDED_OPCODES`;
+- opcodes files from the official 128-bit extension have not been introduced
+  due to the other changes which they imply to other opcodes specifications;
+- some of the instructions originally declared in the vectorial extension
+  (`opcodes-rvv` file) have been set as pseudo-instruction due to the overlapping
+  of their opcodes space with the opcodes space of the SIMD instructions from
+  Xpulpv2, defined in `opcodes-xpulpimg_CUSTOM`.

encoding.h

@@ -12,7 +12,7 @@
 #define MSTATUS_HPIE        0x00000040
 #define MSTATUS_MPIE        0x00000080
 #define MSTATUS_SPP         0x00000100
-#define MSTATUS_HPP         0x00000600
+#define MSTATUS_VS          0x00000600
 #define MSTATUS_MPP         0x00001800
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
@@ -25,13 +25,16 @@
 #define MSTATUS32_SD        0x80000000
 #define MSTATUS_UXL         0x0000000300000000
 #define MSTATUS_SXL         0x0000000C00000000
+#define MSTATUS_GVA         0x0000004000000000
+#define MSTATUS_MPV         0x0000008000000000
 #define MSTATUS64_SD        0x8000000000000000
 
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
 #define SSTATUS_UPIE        0x00000010
 #define SSTATUS_SPIE        0x00000020
 #define SSTATUS_SPP         0x00000100
+#define SSTATUS_VS          0x00000600
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
 #define SSTATUS_SUM         0x00040000
@@ -40,6 +43,24 @@
 #define SSTATUS_UXL         0x0000000300000000
 #define SSTATUS64_SD        0x8000000000000000
 
+#define SSTATUS_VS_MASK     (SSTATUS_SIE | SSTATUS_SPIE | \
+                             SSTATUS_SPP | SSTATUS_SUM | \
+                             SSTATUS_MXR | SSTATUS_UXL)
+
+#define HSTATUS_VSXL        0x300000000
+#define HSTATUS_VTSR        0x00400000
+#define HSTATUS_VTW         0x00200000
+#define HSTATUS_VTVM        0x00100000
+#define HSTATUS_VGEIN       0x0003f000
+#define HSTATUS_HU          0x00000200
+#define HSTATUS_SPVP        0x00000100
+#define HSTATUS_SPV         0x00000080
+#define HSTATUS_GVA         0x00000040
+#define HSTATUS_VSBE        0x00000020
+
+#define USTATUS_UIE         0x00000001
+#define USTATUS_UPIE        0x00000010
+
 #define DCSR_XDEBUGVER      (3U<<30)
 #define DCSR_NDRESET        (1<<29)
 #define DCSR_FULLRESET      (1<<28)
@@ -61,6 +82,7 @@
 #define DCSR_CAUSE_DEBUGINT 3
 #define DCSR_CAUSE_STEP     4
 #define DCSR_CAUSE_HALT     5
+#define DCSR_CAUSE_GROUP    6
 
 #define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
 #define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
@@ -95,24 +117,35 @@
 #define MCONTROL_MATCH_MASK_LOW  4
 #define MCONTROL_MATCH_MASK_HIGH 5
 
+#define MIP_USIP            (1 << IRQ_U_SOFT)
 #define MIP_SSIP            (1 << IRQ_S_SOFT)
-#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_VSSIP           (1 << IRQ_VS_SOFT)
 #define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_UTIP            (1 << IRQ_U_TIMER)
 #define MIP_STIP            (1 << IRQ_S_TIMER)
-#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_VSTIP           (1 << IRQ_VS_TIMER)
 #define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_UEIP            (1 << IRQ_U_EXT)
 #define MIP_SEIP            (1 << IRQ_S_EXT)
-#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_VSEIP           (1 << IRQ_VS_EXT)
 #define MIP_MEIP            (1 << IRQ_M_EXT)
+#define MIP_SGEIP           (1 << IRQ_S_GEXT)
+
+#define MIP_S_MASK          (MIP_SSIP | MIP_STIP | MIP_SEIP)
+#define MIP_VS_MASK         (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
+#define MIP_HS_MASK         (MIP_VS_MASK | MIP_SGEIP)
+
+#define MIDELEG_FORCED_MASK MIP_HS_MASK
 
 #define SIP_SSIP MIP_SSIP
 #define SIP_STIP MIP_STIP
 
 #define PRV_U 0
 #define PRV_S 1
-#define PRV_H 2
 #define PRV_M 3
 
+#define PRV_HS (PRV_S + 1)
+
 #define SATP32_MODE 0x80000000
 #define SATP32_ASID 0x7FC00000
 #define SATP32_PPN  0x003FFFFF
@@ -127,6 +160,19 @@
 #define SATP_MODE_SV57 10
 #define SATP_MODE_SV64 11
 
+#define HGATP32_MODE 0x80000000
+#define HGATP32_VMID 0x1FC00000
+#define HGATP32_PPN 0x003FFFFF
+
+#define HGATP64_MODE 0xF000000000000000
+#define HGATP64_VMID 0x03FFF00000000000
+#define HGATP64_PPN 0x00000FFFFFFFFFFF
+
+#define HGATP_MODE_OFF 0
+#define HGATP_MODE_SV32X4 1
+#define HGATP_MODE_SV39X4 8
+#define HGATP_MODE_SV48X4 9
+
 #define PMP_R     0x01
 #define PMP_W     0x02
 #define PMP_X     0x04
@@ -138,15 +184,19 @@
 #define PMP_NA4   0x10
 #define PMP_NAPOT 0x18
 
+#define IRQ_U_SOFT   0
 #define IRQ_S_SOFT   1
-#define IRQ_H_SOFT   2
+#define IRQ_VS_SOFT  2
 #define IRQ_M_SOFT   3
+#define IRQ_U_TIMER  4
 #define IRQ_S_TIMER  5
-#define IRQ_H_TIMER  6
+#define IRQ_VS_TIMER 6
 #define IRQ_M_TIMER  7
+#define IRQ_U_EXT    8
 #define IRQ_S_EXT    9
-#define IRQ_H_EXT    10
+#define IRQ_VS_EXT   10
 #define IRQ_M_EXT    11
+#define IRQ_S_GEXT   12
 #define IRQ_COP      12
 #define IRQ_HOST     13