[AArch64] armv8-A doesn't have CRC.

That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302077 91177308-0d34-0410-b5e6-96231b3b80d8
multun · May 3, 2017 · 700df98 · 700df98
1 parent 0a73805
commit 700df98
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Showing 7 changed files with 52 additions and 64 deletions.
diff --git a/include/llvm/Support/AArch64TargetParser.def b/include/llvm/Support/AArch64TargetParser.def
@@ -20,8 +20,7 @@ AARCH64_ARCH("invalid", AK_INVALID, nullptr, nullptr,
              ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
 AARCH64_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
              FK_CRYPTO_NEON_FP_ARMV8,
-             (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-              AArch64::AEK_SIMD))
+             (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
 AARCH64_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a",
              ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |

diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td
@@ -358,7 +358,6 @@ def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
                                        FeatureNEON]>;
 
 def : ProcessorModel<"generic", NoSchedModel, [
-                     FeatureCRC,
                      FeatureFPARMv8,
                      FeatureNEON,
                      FeaturePerfMon,

diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s
@@ -1496,23 +1496,6 @@ _func:
 // Data-processing (2 source)
 //------------------------------------------------------------------------------
 
-        crc32b  w5, w7, w20
-        crc32h  w28, wzr, w30
-        crc32w  w0, w1, w2
-        crc32x  w7, w9, x20
-        crc32cb w9, w5, w4
-        crc32ch w13, w17, w25
-        crc32cw wzr, w3, w5
-        crc32cx w18, w16, xzr
-// CHECK: crc32b   w5, w7, w20             // encoding: [0xe5,0x40,0xd4,0x1a]
-// CHECK: crc32h   w28, wzr, w30           // encoding: [0xfc,0x47,0xde,0x1a]
-// CHECK: crc32w   w0, w1, w2              // encoding: [0x20,0x48,0xc2,0x1a]
-// CHECK: crc32x   w7, w9, x20             // encoding: [0x27,0x4d,0xd4,0x9a]
-// CHECK: crc32cb  w9, w5, w4              // encoding: [0xa9,0x50,0xc4,0x1a]
-// CHECK: crc32ch  w13, w17, w25           // encoding: [0x2d,0x56,0xd9,0x1a]
-// CHECK: crc32cw  wzr, w3, w5             // encoding: [0x7f,0x58,0xc5,0x1a]
-// CHECK: crc32cx  w18, w16, xzr           // encoding: [0x12,0x5e,0xdf,0x9a]
-
         udiv	w0, w7, w10
         udiv	x9, x22, x4
         sdiv	w12, w21, w0

diff --git a/test/MC/AArch64/crc.s b/test/MC/AArch64/crc.s
@@ -0,0 +1,45 @@
+// RUN: llvm-mc -triple aarch64-- -mattr=+crc %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=CRC
+
+// RUN: not llvm-mc -triple aarch64-- %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=NOCRC
+// RUN: not llvm-mc -triple aarch64-- -mcpu=cyclone %s 2>&1 |\
+// RUN:   FileCheck %s --check-prefix=NOCRC
+
+    crc32b w0, w1, w5
+    crc32h w3, w5, w6
+    crc32w w19, wzr, w20
+    crc32x w3, w5, x20
+
+// CRC: crc32b w0, w1, w5
+// CRC: crc32h w3, w5, w6
+// CRC: crc32w w19, wzr, w20
+// CRC: crc32x w3, w5, x20
+
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32b w0, w1, w5
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32h w3, w5, w6
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32w w19, wzr, w20
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32x w3, w5, x20
+
+    crc32cb w5, w10, w15
+    crc32ch w3, w5, w7
+    crc32cw w11, w13, w17
+    crc32cx w19, w23, x29
+
+// CRC: crc32cb w5, w10, w15
+// CRC: crc32ch w3, w5, w7
+// CRC: crc32cw w11, w13, w17
+// CRC: crc32cx w19, w23, x29
+
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32cb w5, w10, w15
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32ch w3, w5, w7
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32cw w11, w13, w17
+// NOCRC: error: instruction requires: crc
+// NOCRC:     crc32cx w19, w23, x29
diff --git a/test/MC/AArch64/cyclone-crc.s b/test/MC/AArch64/cyclone-crc.s
diff --git a/test/MC/AArch64/directive-arch-negative.s b/test/MC/AArch64/directive-arch-negative.s
@@ -44,6 +44,12 @@
 # CHECK: error: instruction requires: lse
 # CHECK:        casa  w5, w7, [x19]
 
+	.arch armv8+crypto
+        crc32b w0, w1, w2
+
+# CHECK: error: instruction requires: crc
+# CHECK:        crc32b w0, w1, w2
+
 	.arch armv8.1-a+nolse
         casa  w5, w7, [x20]
 

diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -1042,23 +1042,6 @@
 # Data-processing (2 source)
 #------------------------------------------------------------------------------
 
-# CHECK: crc32b  w5, w7, w20
-# CHECK: crc32h  w28, wzr, w30
-# CHECK: crc32w  w0, w1, w2
-# CHECK: crc32x  w7, w9, x20
-# CHECK: crc32cb w9, w5, w4
-# CHECK: crc32ch w13, w17, w25
-# CHECK: crc32cw wzr, w3, w5
-# CHECK: crc32cx w18, w16, xzr
-0xe5 0x40 0xd4 0x1a
-0xfc 0x47 0xde 0x1a
-0x20 0x48 0xc2 0x1a
-0x27 0x4d 0xd4 0x9a
-0xa9 0x50 0xc4 0x1a
-0x2d 0x56 0xd9 0x1a
-0x7f 0x58 0xc5 0x1a
-0x12 0x5e 0xdf 0x9a
-
 # CHECK: udiv	w0, w7, w10
 # CHECK: udiv	x9, x22, x4
 # CHECK: sdiv	w12, w21, w0