[AArch64][SVE] Asm: More concise test format

Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file.

The tests check the following:

 * All instructions are assembled correctly into the right encoding.
 * All instructions are disassembled correctly (into the preferred assembly format)
 * Without -mattr=+sve the instructions are not assembled.
 * Without -mattr=+sve the instructions are not disassembled.

This patch also adds several negative tests for SVE add/sub.


Patch by Sander De Smalen.

Reviewed by: rengolin, fhahn

Differential Revision: https://reviews.llvm.org/D39792


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317894 91177308-0d34-0410-b5e6-96231b3b80d8

test/MC/AArch64/SVE/add-diagnostics.s

@@ -0,0 +1,16 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Register z32 does not exist.
+add z22.h, z10.h, z32.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: add z22.h, z10.h, z32.h
+
+// Invalid element kind.
+add z20.h, z2.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: add z20.h, z2.h, z31.x
+
+// Element size specifiers should match.
+add z27.h, z11.h, z27.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: add z27.h, z11.h, z27.b

test/MC/AArch64/SVE/add.s

@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+add     z31.s, z31.s, z31.s
+// CHECK-INST: add     z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x03,0xbf,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: ff 03 bf 04 <unknown>
+
+add     z23.d, z13.d, z8.d
+// CHECK-INST: add     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x01,0xe8,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: b7 01 e8 04 <unknown>
+
+add     z0.s, z0.s, z0.s
+// CHECK-INST: add     z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x00,0xa0,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 00 00 a0 04 <unknown>
+
+add     z31.d, z31.d, z31.d
+// CHECK-INST: add     z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x03,0xff,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: ff 03 ff 04 <unknown>
+
+add     z21.b, z10.b, z21.b
+// CHECK-INST: add     z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0x01,0x35,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 55 01 35 04 <unknown>
+
+add     z31.b, z31.b, z31.b
+// CHECK-INST: add     z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x03,0x3f,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: ff 03 3f 04 <unknown>
+
+add     z0.h, z0.h, z0.h
+// CHECK-INST: add     z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x00,0x60,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 00 00 60 04 <unknown>
+
+add     z23.b, z13.b, z8.b
+// CHECK-INST: add     z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0x01,0x28,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: b7 01 28 04 <unknown>
+
+add     z0.d, z0.d, z0.d
+// CHECK-INST: add     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x00,0xe0,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 00 00 e0 04 <unknown>
+
+add     z31.h, z31.h, z31.h
+// CHECK-INST: add     z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x03,0x7f,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: ff 03 7f 04 <unknown>
+
+add     z0.b, z0.b, z0.b
+// CHECK-INST: add     z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x00,0x20,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 00 00 20 04 <unknown>
+
+add     z21.d, z10.d, z21.d
+// CHECK-INST: add     z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0x01,0xf5,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 55 01 f5 04 <unknown>
+
+add     z21.h, z10.h, z21.h
+// CHECK-INST: add     z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x01,0x75,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 55 01 75 04 <unknown>
+
+add     z21.s, z10.s, z21.s
+// CHECK-INST: add     z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0x01,0xb5,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: 55 01 b5 04 <unknown>
+
+add     z23.h, z13.h, z8.h
+// CHECK-INST: add     z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x01,0x68,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: b7 01 68 04 <unknown>
+
+add     z23.s, z13.s, z8.s
+// CHECK-INST: add     z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0x01,0xa8,0x04]
+// CHECK-ERROR: invalid operand for instruction
+// CHECK-UNKNOWN: b7 01 a8 04 <unknown>

test/MC/AArch64/SVE/sub-diagnostics.s

@@ -0,0 +1,16 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// Register z32 does not exist.
+sub z3.h, z26.h, z32.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sub z3.h, z26.h, z32.h
+
+// Invalid element kind.
+sub z4.h, z27.h, z31.x
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
+// CHECK-NEXT: sub z4.h, z27.h, z31.x
+
+// Element size specifiers should match.
+sub z0.h, z8.h, z8.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sub z0.h, z8.h, z8.b